DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet
DSPIC30F3010-20I/SP
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DSPIC30F3010-20I/SP Summary of contents
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... Family Silicon Errata and Data Sheet Clarification The dsPIC30F3010/3011 family devices that you have received conform functionally to the current Device Data Sheet (DS70141E), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in 2010 ...
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... TABLE 2: SILICON ISSUE SUMMARY Item Module Feature Number CPU MAC Class 1. Instructions with ±4 Address Modification CPU 2. DAW.b Instruction PSV Using SR 3. Operations PSV — 4. Operations PLL 4x Mode 5. CPU Early 6. Termination of Nested DO Loops Interrupt — 7. Controller CPU 8. DISI Instruction 32 kHz Sleep Mode 9 ...
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... Consumption in Sleep Mode Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Issue Summary 2 When the I C module is enabled, the dsPIC generates a glitch on the SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration ...
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... Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A2). 1. Module: CPU Sequential MAC class instructions, which prefetch data from Y data space using ± ...
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... Example 2 is demonstrated in Example 3. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 These instructions are identified in Table 3. Example 2 demonstrates a scenario where this occurs. Also, always use work around 2 if the C compiler is used to generate code for dsPIC30F3010/3011 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 ...
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... Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: • MOV.D • Register Indirect Addressing (word or byte mode) with pre/post-decrement Work around Do not perform PSV accesses to any of the first four bytes using the above addressing modes ...
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... There is one level of DISI, so this macro saves and restores the DISI state. For temporarily modifying and restoring the CPU IPL, the mac- ros RESTORE_CPU_IPL can be used, as shown in Example 7. These macros also make use of the SET_CPU_IPL macro. dsPIC30F3010/3011 USING SET_CPU_IPL MACRO \ \ and SET_AND_SAVE_CPU_IPL ...
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... For modification of the Interrupt 1 setting, the INTERRUPT_PROTECT macro can be used. This macro disables interrupts before executing the desired expression, as shown in Example 8. This macro is not distributed with the compiler. EXAMPLE 8: USING INTERRUPT_PROTECT MACRO #define INTERRUPT_PROTECT ( int save_sr; \ SET_AND_SAVE_CPU_IPL (save_sr, 7);\ x; \ RESTORE_CPU_IPL (save_sr); } (void) 0; ...
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... © 2010 Microchip Technology Inc. dsPIC30F3010/3011 9. Module: 32 kHz Low-Power (LP) Oscillator The LP oscillator is located on the SOSCO and SOSCI device pins and serves as a secondary crystal clock source for low-power operation. The LP oscillator can also drive Timer1 for a real-time clock application. The LP oscillator does not function when the device is placed in Sleep mode ...
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... Module: Output Compare A glitch will be produced on an output compare pin under the following conditions: • The user software initially drives the I/O pin high using the output compare module or a write to the associated PORT register. • The output compare module is configured ...
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... Up to 256. 300 ksps Work around None. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F3010/3011 R Max V Temperature S DD 500Ω 4.5V to 5.5V -40°C to +85°C 5.0 kΩ 4.5V to 5.5V -40°C to +125°C 5.0 kΩ 3.0V to 5.5V -40°C to +125°C ...
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... Module: QEI The QEI module does not generate an interrupt when MAXCNT is set to 0xFFFF and the following events occur: 1. POSCNT underflows from 0x0000 to 0xFFFF. 2. POSCNT stops. 3. POSCNT overflows from 0xFFFF to 0x0000. This sequence of events occurs when the motor is running in one direction, which causes POSCNT to underflow to 0xFFFF ...
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... © 2010 Microchip Technology Inc. dsPIC30F3010/3011 18. Module 10-bit Addressing mode, some address matches don’t set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses. In particular, these include all addresses with the form XX0000XXXX following exceptions: • ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... REF Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F3010/3011 24. Module: PWM If the PTDIR bit is set (when PTMR is counting down), and the CPU execution is halted (after a breakpoint is reached), PTMR will start counting PTDIR was zero. Work around None. Affected Silicon Revisions ...
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... Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, implement any of the following three work arounds, depending on the application requirements ...
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... LP Oscillator crystal. Affected Silicon Revisions © 2010 Microchip Technology Inc. dsPIC30F3010/3011 28. Module: QEI When the TQCS and TQGATE bits in the QEIxCON register are set, a QEI interrupt should be generated after an input pulse on the QEA input. This interrupt is not generated in the affected silicon. the ...
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... Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70141E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: DC Characteristics: I/O Pin Input ...
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... C), 22 (I/O Port), 23 (ADC), 24 (PWM), 25 (Timer), 26 (PLL) and 27 (Sleep Mode). This document replaces the following errata documents: • DS80216, “dsPIC30F3010/3011 Rev. A0/A1 Silicon Errata” • DS80389, “dsPIC30F3010/3011 Rev. A2 Silicon Errata” Rev B Document (8/2009) Updated silicon issue 7 (Interrupt Controller). ...
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... NOTES: DS80449D-page 20 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 01/05/10 ...