DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet
DSPIC30F3010-20I/SP
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DSPIC30F3010-20I/SP Summary of contents
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... Microchip Technology Inc. dsPIC30F3010/3011 Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70141E ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Single-Cycle Hardware Fractional/ Integer Multiplier • All DSP Instructions Single Cycle • ±16-Bit Single-Cycle Shift © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Peripheral Features: • High-Current Sink/Source I/O Pins: 25 mA/25 mA • Timer module with Programmable Prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...
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... Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes dsPIC30F Motor Control and Power Conversion Family Program SRAM Device Pins Mem. Bytes/ Bytes Instructions dsPIC30F3010 28 24K/8K 1024 dsPIC30F3011 40/44 24K/8K 1024 DS70141E-page 2 CMOS Technology: • Low-Power, High-Speed Flash Technology • ...
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... PDIP EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 44-Pin TQFP PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 RF1 RF0 V V PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 MCLR +/CN2/RB0 REF SS -/CN3/RB1 3 38 PWM1L/RE0 REF 4 37 PWM1H/RE1 5 36 PWM2L/RE2 6 ...
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... Pin Diagrams (Continued) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 DS70141E-page RF1 5 29 RF0 dsPIC30F3011 OSC2/CLKO/RC15 OSC1/CLKI AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 © 2008 Microchip Technology Inc. ...
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... OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 3 26 PWM1H/RE1 4 25 PWM2L/RE2 5 24 PWM2H/RE3 6 23 PWM3L/RE4 PWM3H/RE5 SS OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/RF2 11 18 PGD/EMUD/U1TX/SDO1/SCL/RF3 FLTA/INT0/SCK1/OCFA/RE8 EMUC2/OC1/IC1/INT1/RD0 dsPIC30F3010 OSC2/CLKO/RC15 OSC1/CLKI AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 DS70141E-page 5 ...
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... Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU Architecture Overview........................................................................................................................................................ 15 3.0 Memory Organization ................................................................................................................................................................. 23 4.0 Address Generator Units ............................................................................................................................................................ 35 5.0 Interrupts .................................................................................................................................................................................... 41 6.0 Flash Program Memory .............................................................................................................................................................. 47 7.0 Data EEPROM Memory ............................................................................................................................................................. 53 8.0 I/O Ports ..................................................................................................................................................................................... 59 9.0 Timer1 Module ........................................................................................................................................................................... 65 10.0 Timer2/3 Module ........................................................................................................................................................................ 69 11.0 Timer4/5 Module ....................................................................................................................................................................... 75 12.0 Input Capture Module ................................................................................................................................................................. 79 13 ...
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... Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for the dsPIC30F3011 and dsPIC30F3010 devices. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The dsPIC30F DS70141E-page 7 ...
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... FIGURE 1-1: dsPIC30F3011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH PCL Program Counter Loop Stack Address Latch Control Control Logic Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...
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... FIGURE 1-2: dsPIC30F3010 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCL PCU Program Counter Stack Loop Address Latch Control Control Logic Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...
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... Table 1-1 provides a brief description of the device I/O pinout and the functions that are multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...
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... Schmitt Trigger input with CMOS levels I = Input © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. In-Circuit Serial Programming™ data input/output pin. ...
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... Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-2: dsPIC30F3010 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type ...
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... TABLE 1-2: dsPIC30F3010 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB5 I/O ST RC13-RC15 8I/O 8ST RD0-RD1 I/O ST RE0-RE5, I/O ST RE8 RF2-RF3 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SCL ...
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... NOTES: DS70141E-page 14 © 2008 Microchip Technology Inc. ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. ...
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... Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16x16-bit working registers (W0 through W15), 2x40-bit accumulators (ACCA and ACCB), STATUS Register (SR), Data Table Page register (TBLPAG), Program Space Visibility Page register (PSVPAG), DO and REPEAT registers (DOSTART, DOEND, DCOUNT and RCOUNT) and Program Coun- ter (PC) ...
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... DSP ACCA Accumulators ACCB PC22 TBLPAG Data Table Page Address PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. dsPIC30F3010/3011 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 Program Space Visibility Page Address ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: 1. DIVF – 16/16 signed fractional divide 2. DIV.sd – ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2008 Microchip Technology Inc. dsPIC30F3010/3011 40-Bit Accumulator A 40-Bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70141E-page 19 ...
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... MULTIPLIER The 17x17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value ...
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... If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a ...
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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
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... Device ID, the User ID and the Configuration bits; otherwise, bit 23 is always clear. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F3010/3011 Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-2: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using 0 PSVPAG Reg Program Space ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2008 Microchip Technology Inc. dsPIC30F3010/3011 A set of table instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; ...
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... FIGURE 3-4: PROGRAM DATA TABLE ACCESS (MSB) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 Program Memory ‘Phantom’ Byte (Read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Program Space 0x0000 (1) PSVPAG 0x00 8 ...
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... FIGURE 3-6: dsPIC30F3010/3011 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 1 Kbyte 0x09FF 0x0A01 SRAM Space 0x0BFF 0x0C01 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70141E-page 28 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA Using any W © 2008 Microchip Technology Inc. dsPIC30F3010/3011 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read-Only Indirect EA Using W10, W11Indirect EA Using W8, W9 ...
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... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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... DS70141E-page 32 © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 33 ...
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... NOTES: DS70141E-page 34 © 2008 Microchip Technology Inc. ...
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... Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2008 Microchip Technology Inc. dsPIC30F3010/3011 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP Accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2008 Microchip Technology Inc. dsPIC30F3010/3011 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags, as well register field to specify the W address registers. The XWM and YWM fields select which registers will operate with Modulo Addressing ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W regis- ter important to realize that the address boundar- ies check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decre- menting buffers) boundary addresses (not just equal to) ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 512 256 128 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Decimal XB<14:0> Bit-Reversed Address Modifier Value Bit-Reversed Address A0 Decimal 0x0100 0x0080 0x0040 ...
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... NOTES: DS70141E-page 40 © 2008 Microchip Technology Inc. ...
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... For more information on the device instruction set and programming, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). The dsPIC30F3010/3011 has 29 interrupt sources and 4 processor exceptions (traps), which must be arbitrated based on a priority scheme. The CPU is responsible for reading the Interrupt Vector Table (IVT) and transferring the address con- tained in the interrupt vector to the program counter ...
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... Interrupt Priority The user-assignable Interrupt Priority (IP<2:0>) bits for each individual interrupt source are located in the 3 LSbs of each nibble, within the IPCx register(s). Bit 3 of each nibble is not used and is read as a ‘0’. These bits define the priority level assigned to a particular interrupt by the user ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 5.3 Traps Traps can be considered as non-maskable interrupts, indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1. They ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...
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... ISR uses fast context saving. 5.7 External Interrupt Requests The dsPIC30F3010/3011 interrupt controller supports three external interrupt request signals, INT0-INT2. These inputs are edge sensitive; they require a low-to- high or a high-to-low transition to generate an interrupt request. The INTCON2 register has five bits, INT0EP- INT4EP, that select the polarity of the edge detection circuitry ...
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... DS70141E-page 46 © 2008 Microchip Technology Inc. ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F3010/3011 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions or 96 bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program 32 instructions at one time. ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F3010/3011 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 51 ...
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... NOTES: DS70141E-page 52 © 2008 Microchip Technology Inc. ...
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... NVMADRU register, is used to address the EEPROM location being accessed. TBLRDL and TBLWTL instruc- tions are used to read and write data EEPROM. The dsPIC30F3010/3011 devices have 1 Kbyte (512 words) of data EEPROM, with an address range from 0x7FFC00 to 0x7FFFFE. A word write operation should be preceded by an erase of the corresponding memory location(s) ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON reg- ister ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 [ W0]++ TBLWTL W2 , MOV #data2,W2 ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70141E-page 58 © 2008 Microchip Technology Inc. ...
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... WR PORT Read LAT Read PORT © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins, and writes to the port pins, write the latch (LATx). Any bit and its associated data and control registers that are not valid for a particular device will be disabled ...
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... FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module Read TRIS Data Bus WR TRIS TRIS Latch WR LAT + WR PORT Data Latch Read LAT Read PORT 8.2 ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 61 ...
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... DS70141E-page 62 © 2008 Microchip Technology Inc. ...
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... CNEN1 00C0 CN7IE CN6IE CN5IE CNPU1 00C4 CN7PUE CN6PUE CN5PUE Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Bit 5 Bit 4 Bit 3 Bit 2 CN4IE CN3IE CN2IE CN4PUE CN3PUE CN2PUE CN1PUE (1) Bit 1 ...
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... NOTES: DS70141E-page 64 © 2008 Microchip Technology Inc. ...
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... Interrupt on 16-bit Period register match or falling edge of external gate signal © 2008 Microchip Technology Inc. dsPIC30F3010/3011 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-Bit Timer Mode: In the 16-Bit Timer mode, the ...
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... FIGURE 9-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Reset 0 T1IF Event Flag 1 TGATE SOSCO/ T1CK LPOSCEN SOSCI 9.1 Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit, TGATE (T1CON< ...
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... XTAL SOSCO pF 100K © 2008 Microchip Technology Inc. dsPIC30F3010/3011 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register, and is then reset to ‘0’. ...
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... DS70141E-page 68 © 2008 Microchip Technology Inc. ...
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... These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. Note: For 32-bit timer operation, T3CON control bits are ignored ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD 16 Write TMR2 Read TMR2 16 Reset TMR3 MSB ADC Event Trigger Comparator x 32 Equal PR3 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit, T32 T2CON(<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
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... Comparator x 16 Reset 0 T3IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer3. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2008 Microchip Technology Inc. dsPIC30F3010/3011 PR2 TMR2 ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 73 ...
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... NOTES: DS70141E-page 74 © 2008 Microchip Technology Inc. ...
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... Timer configuration bit, T32 T4CON(<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © ...
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... TIMER4 BLOCK DIAGRAM (TYPE B TIMER) Equal Comparator x 16 Reset 0 T4IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) DS70141E-page 76 PR4 TMR4 Q D TGATE ...
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... Reset 0 T5IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2008 Microchip Technology Inc. dsPIC30F3010/3011 PR5 Comparator x 16 ...
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... DS70141E-page 78 © 2008 Microchip Technology Inc. ...
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... Interrupt on input capture event These operating modes are determined by setting the appropriate bits in the ICxCON register (where x = 1,2,...,N). Note: The dsPIC30F3010/3011 devices have four capture channels. The channels are designated IC1, IC2, IC7 and IC8 to maintain software compatibility with other dsPIC30F devices. ...
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... Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • Capture every falling edge • Capture every rising edge • Capture every 4th rising edge • Capture every 16th rising edge • Capture every rising and falling edge These simple Input Capture modes are configured by setting the appropriate bits, ICM< ...
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... If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt based upon the selected number of capture events. The selection number is set by control bits, ICI< ...
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... DS70141E-page 82 © 2008 Microchip Technology Inc. ...
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... Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC30F3010/3011 devices have 4/2 compare channels, respectively. OCxRS and OCxR in the figure represent the Dual Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers: Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.2 Simple Output Compare Match Mode When control bits, OCM< ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • ...
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... DS70141E-page 86 © 2008 Microchip Technology Inc. ...
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... Programmable INDX Digital Filter 3 Note 1: In dsPIC30F3010/3011, the UPDN pin is not available. Up/Down logic bit can still be polled by software. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...
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... Quadrature Encoder Interface Logic A typical incremental (a.k.a. optical) encoder has three outputs: Phase A, Phase B and an index pulse. These signals are useful and often required in position and speed control of ACIM and SR motors. The two channels, Phase A (QEA) and Phase B (QEB), have a unique relationship ...
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... To enable the filter output for channels, QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 14.5 Alternate 16-Bit Timer/Counter When the QEI module is not configured for the QEI mode, QEIM< ...
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... QEI Module Operation During CPU Idle Mode Since the QEI module can function as a Quadrature Encoder Interface 16-bit timer, the following section describes operation of the module in both modes. 14.7.1 QEI OPERATION DURING CPU IDLE MODE When the CPU is placed in the Idle mode, the QEI ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 91 ...
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... NOTES: DS70141E-page 92 © 2008 Microchip Technology Inc. ...
Page 95
... The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution © 2008 Microchip Technology Inc. dsPIC30F3010/3011 • ‘On-the-Fly’ PWM frequency changes • Edge and Center-Aligned Output modes • Single Pulse Generation mode • ...
Page 96
... FIGURE 15-1: PWM MODULE BLOCK DIAGRAM PWMCON1 PWMCON2 DTCON1 FLTACON OVDCON PTMR Comparator PTPER PTPER Buffer PTCON Comparator SEVTDIR SEVTCMP PWM Time Base Note: Details of PWM Generator #1 and #2 not shown for clarity. DS70141E-page 94 PWM Enable and Mode SFRs Dead-Time Control SFRs ...
Page 97
... The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 15.1.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched ...
Page 98
... DOUBLE-UPDATE MODE In the Double-Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR regis- ter is equal to zero, as well as each time a period match occurs. The postscaler selection bits have no effect in this mode of the timer. The Double-Update mode provides two additional functions to the user ...
Page 99
... PWM period. In addition, the out- put on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to the value held in the PTPER register. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 15-3: CENTER-ALIGNED PWM Period/2 PTPER ...
Page 100
... When the PWM time base is in the Continuous Up/ Down Count mode with double updates, new duty cycle values are updated when the value of the PTMR regis- ter is zero, and when the value of the PTMR register matches the value in the PTPER register. The contents ...
Page 101
... FIGURE 15-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Dead Time © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Dead Time DS70141E-page 99 ...
Page 102
... Independent PWM Output An Independent PWM Output mode is required for driving certain types of loads. A particular PWM output pair is in the Independent Output mode when the corresponding PMOD bit in the PWMCON1 register is set. No dead-time control is implemented between adjacent PWM I/O pins when the module is operating in the Independent mode and both I/O pins are allowed to be active simultaneously ...
Page 103
... The Fault pin has an interrupt vector, interrupt flag bit and interrupt priority bits associated with it. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 15.12.2 FAULT STATES The FLTACON Special Function Register has 6 bits that determine the state of each PWM I/O pin when it is overridden by a Fault input ...
Page 104
... PWM Update Lockout For a complex PWM application, the user may need to write up to three Duty Cycle registers and the Time Base Period register, PTPER given time. In some applications important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 103 ...
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... NOTES: DS70141E-page 104 © 2008 Microchip Technology Inc. ...
Page 107
... If any trans- mit data has been written to the buffer register, the © 2008 Microchip Technology Inc. dsPIC30F3010/3011 contents of the transmit buffer are moved to SPI1SR. The received data is thus placed in SPI1BUF and the transmit data in SPI1SR is ready for the next transfer. ...
Page 108
... Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit, FRMEN, enables framed SPI support and causes the SS1 pin to perform the Frame Synchronization (F function. The control bit, SPIFSD, determines whether FIGURE 16-1: ...
Page 109
... Therefore, when the SS1 pin is asserted low again, transmission/reception will begin at the MSb, even if SS1 has been deasserted in the middle of a transmit/receive. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down. If ...
Page 110
... DS70141E-page 108 © 2008 Microchip Technology Inc. ...
Page 111
... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 17.1.1 VARIOUS I The following types • Slave operation with 7-bit addressing 2 • Slave operation with 10-bit addressing 2 • ...
Page 112
... FIGURE 17-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70141E-page 110 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload ...
Page 113
... ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated. Incoming bits are sampled on the rising edge of SCL ...
Page 114
... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion, with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 17.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 115
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device-specific general call address. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 2 17. Master Support As a master device, six operations are supported Slave • ...
Page 116
... I C MASTER RECEPTION Master mode reception is enabled by programming the Receive Enable (RCEN) bit (I2CCON<3>). The I module must be Idle before the RCEN bit is set; other- wise, the RCEN bit will be disregarded. The Baud Rate Generator begins counting, and on each rollover, the state of the SCL pin toggles, and data is shifted into the I2CRSR on the rising edge of each clock ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 115 ...
Page 118
... NOTES: DS70141E-page 116 © 2008 Microchip Technology Inc. ...
Page 119
... Internal Data Bus UTXBRK Data UxTX Parity Note dsPIC30F3010 only has UART1. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • ...
Page 120
... FIGURE 18-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70141E-page 118 Internal Data Bus 16 Write Read UxRXREG Low Byte URX8 Receive Buffer Control – ...
Page 121
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F3010/3011 18.3 Transmitting Data 18.3.1 TRANSMITTING IN 8-BIT DATA MODE ...
Page 122
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding Interrupt Flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 123
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables the Address Detect mode, in which a 9th bit (URX8) value of ‘ ...
Page 124
... Auto Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input. To enable this mode, the user must program the input capture module to detect the falling and rising edges of the Start bit. ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 123 ...
Page 126
... NOTES: DS70141E-page 124 © 2008 Microchip Technology Inc. ...
Page 127
... REF REF being able to operate while the device is in Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select register (ADCHS) • ...
Page 128
... AN5 AN8 AN0 AN1 AN2 AN3 AN3 AN4 AN4 AN5 AN5 AN6 (1) AN6 AN7 (1) AN7 AN8 (1) AN8 AN1 Note 1: Not available on dsPIC30F3010 devices. DS70141E-page 126 + CH1 ADC S/H - 10-Bit Result + CH2 S/H - 16-word, 10-bit Dual Port + CH3 S/H CH1,CH2, - CH3,CH0 Sample/Sequence ...
Page 129
... SIMSAM bit is not applicable. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 The CHPS bits select how many channels are sam- pled. This can vary from channels. If the CHPS bits select 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
Page 130
... Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to five alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control ...
Page 131
... Up to 256. 300 ksps Note 1: External V - and V + pins must be used for correct operation. See Figure 19-2 for recommended REF REF circuit. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Table 19-1 R Max V Temperature S DD 500Ω 4.5V to 5.5V -40°C to +85°C 500Ω ...
Page 132
... The configuration guidelines give the required setup values for the conversion speeds above 500 ksps, since they require external V pins usage and there REF are some differences in the configuration procedure. Configuration details that are not critical to the conversion speed have been omitted. ...
Page 133
... ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time writing: SAMC<4:0> = 00010 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 19.7.3 600 ksps CONFIGURATION GUIDELINE The configuration for 600 ksps operation is dependent on whether a single input pin sampled or whether multiple pins will be sampled. ...
Page 134
... A/D Acquisition Requirements The analog input model of the 10-bit ADC is shown in Figure 19-3. The total sampling time for the ADC is a function of the internal amplifier settling time, device V and the holding capacitor charge time. DD For the ADC to meet its specified accuracy, the Charge ...
Page 135
... Integer 0 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the ADC module will then be turned off, although the ADON bit will remain set ...
Page 136
... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared ...
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... Microchip Technology Inc. dsPIC30F3010/3011 DS70141E-page 135 ...
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... NOTES: DS70141E-page 136 © 2008 Microchip Technology Inc. ...
Page 139
... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 140
... TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2. XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled. XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled. XT w/PLL 16x 4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 141
... OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F3010/3011 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer Clock ...
Page 142
... Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups, b) and FPR<4:0> Configuration bits that select one of 15 oscillator choices within the primary group. ...
Page 143
... Table 20-4). If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multiplier (respectively) is applied © 2008 Microchip Technology Inc. dsPIC30F3010/3011 . Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7 ...
Page 144
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (Clock Switch and Monitor Selection bits) in the FOSC Con- figuration register. If the FSCM function is enabled, the ...
Page 145
... Reset The dsPIC30F3010/3011 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Reset cause by trap lockup (TRAPR) h) Reset caused by illegal opcode using an ...
Page 146
... FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 147
... The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 148
... Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 20-5: ...
Page 149
... These are: Sleep and Idle. The format of the PWRSAV instruction is as follows: PWRSAV <parameter>, where ‘parameter’ defines Idle or Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 20.5.1 SLEEP MODE In Sleep mode, the clock to the CPU and peripherals is shut down on-chip oscillator is being used shut down ...
Page 150
... Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The proces- sor will process the interrupt and branch to the ISR. The SLEEP status bit in RCON register is set upon wake-up. ...
Page 151
... These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 In each case, the selected EMUD pin is the Emulation/ Debug Data line, and the EMUC pin is the Emulation/ Debug Clock line. These pins will interface to the MPLAB ICD 2 module available from Microchip ...
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... DS70141E-page 150 © 2008 Microchip Technology Inc. ...
Page 153
... The destination, which could either be the File register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modi- fier) or File register (specified by the value of ‘ ...
Page 154
... Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (uncondi- ...
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... Y data space Prefetch Address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space Prefetch Destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Description DS70141E-page 153 ...
Page 156
... TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 157
... DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws< ...
Page 158
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R ...
Page 159
... SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 © 2008 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd+1, Wnd} = unsigned(Wb) * ...
Page 160
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # f,WREG SL Ws,Wd SL Wb,Wns,Wnd SL Wb,#lit5,Wnd 72 SUB SUB Acc SUB f SUB f,WREG SUB #lit10,Wn SUB Wb,Ws,Wd SUB Wb,#lit5,Wd 73 SUBB SUBB f SUBB f,WREG SUBB #lit10,Wn SUBB Wb,Ws,Wd SUBB Wb,#lit5,Wd 74 SUBR ...
Page 161
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F3010/3011 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 162
... MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 163
... Microchip Technology Inc. dsPIC30F3010/3011 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 164
... PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 165
... Microchip Technology Inc. dsPIC30F3010/3011 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ...................................................................................................± pin, inducing currents greater than 80 mA, may cause latch-up. ...
Page 166
... TABLE 23-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F301X-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F301X-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: × – ∑ INT I/O Pin power dissipation × ∑ ...
Page 167
... All I/O pins are configured as inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, program memory and data memory DD are operational. No peripheral modules are operating. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ ...
Page 168
... TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1,2) Typical Max No. Operating Current ( DC51a 1.1 1.8 DC51b 1.1 1.8 DC51c 1.1 1.8 DC51e 2.6 4.0 DC51f 2.4 4.0 DC51g 2.3 4.0 DC50a 3.2 5.0 DC50b 3.3 5.0 DC50c 3.3 5.0 DC50e 6 ...
Page 169
... These values represent the difference between the base power-down current and the power-down current with the specified peripheral enabled during Sleep. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...
Page 170
... TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Input Low Voltage IL DI10 I/O Pins: with Schmitt Trigger Buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 171
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) Reset (due to BOR) © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min Typ ...
Page 172
... TABLE 23-10: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. BO10 V BOR Voltage on V BOR Transition (2) High-to-Low BO15 V BHYS Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. ...
Page 173
... LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Pin FIGURE 23-3: EXTERNAL CLOCK TIMING Q4 OSC1 CLKO © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Operating voltage V range as described DD in Section 23.1 " ...
Page 174
... TABLE 23-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OS10 F External CLKI Frequency OSC (External clocks allowed only in EC mode) Oscillator Frequency OS20 1/F OSC OSC OSC OS25 T Instruction Cycle Time CY OS30 TosL, External Clock in (OSC1) (2) TosH High or Low Time ...
Page 175
... Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ (1) ...
Page 176
... TABLE 23-16: INTERNAL CLOCK TIMING EXAMPLES Clock F OSC Oscillator T CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F DS70141E-page 174 (3) (3) MIPS MIPS (2) (μsec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1.0 4 ...
Page 177
... TABLE 23-18: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2008 Microchip Technology Inc. dsPIC30F3010/3011 -40°C ≤ -40°C ≤ Min Typ Max Units (1) -40°C ≤ T — — ...
Page 178
... FIGURE 23-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 23-2 for load conditions. TABLE 23-19: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port Output Rise Time IO DO32 ...
Page 179
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 23-1 and Table 23-10 for BOR. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 SY10 SY13 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 180
... FIGURE 23-6: BAND GAP START-UP TIME CHARACTERISTICS 0V (1) Enable Band Gap Note 1: Band gap is enabled when FBORPOR<7> is set. TABLE 23-21: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY40 T Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 181
... Frequency Range (oscillator enabled by setting bit, TCS (T1CON<1>)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 182
... TABLE 23-23: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TB10 TtxH TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period TB20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment TABLE 23-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS ...
Page 183
... TQ20 T Delay from External TQCK Clock CKEXTMRL Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 TQ11 TQ10 TQ15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 184
... FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS IC X Note: Refer to Figure 23-2 for load conditions. TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...
Page 185
... Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max Units — ...
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... FIGURE 23-12: MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS FLTA/B MP20 PWMx FIGURE 23-13: MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS PWMx Note: Refer to Figure 23-2 for load conditions. TABLE 23-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
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... These parameters are characterized but not tested in manufacturing Index Channel Digital Filter Clock Divide Select bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” in the”dsPIC30F Family Reference Manual” (DS70046). © 2008 Microchip Technology Inc. dsPIC30F3010/3011 TQ36 TQ30 TQ31 TQ35 TQ41 ...
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... FIGURE 23-15: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS QEA (input) QEB (input) Ungated Index TQ51 Index Internal Position TABLE 23-31: QEI INDEX PULSE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TQ50 TqIL Filter Time to Recognize Low, with Digital Filter TQ51 TqiH ...
Page 189
... These parameters are characterized but not tested in manufacturing. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 3: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 SP10 SP21 SP20 SP20 SP21 MSb ...
Page 190
... FIGURE 23-17: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) SDO MSb X SP40 SP30,SP31 SDI MSb IN X SP41 Note: Refer to Figure 23-2 for load conditions. TABLE 23-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS ...
Page 191
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 SP70 SP72 SP73 SP72 SP73 MSb ...
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... FIGURE 23-19: SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb In SP41 SP40 Note: Refer to Figure 23-2 for load conditions. DS70141E-page 190 SP70 SP73 SP72 SP35 SP73 SP72 ...
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... The minimum clock period for SCx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...
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... FIGURE 23-20: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL IM31 IM30 SDA Start Condition Note: Refer to Figure 23-2 for load conditions. 2 FIGURE 23-21: I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 ...
Page 195
... BRG is the value of the I C™ Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit (I in the”dsPIC30F Family Reference Manual” (DS70046). 2: Maximum pin capacitance = 10 pF for all I © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...
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... FIGURE 23-22: I C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL IS31 IS30 SDA Start Condition 2 FIGURE 23-23: I C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out 2 TABLE 23-37: I C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) ...
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... IS50 C Bus Capacitive B Loading Note 1: Maximum pin capacitance = 10 pF for all I © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended ...
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... TABLE 23-38: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol Characteristic No. AD01 AV Module V Supply DD DD AD02 AV Module V Supply SS SS AD05 V Reference Voltage High REFH AD06 V Reference Voltage Low REFL AD07 V Absolute Reference Voltage AV REF AD08 I Current Drain REF AD10 V -V Full-Scale Input Span ...
Page 199
... Measurements taken with external V 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min ...
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... FIGURE 23-24: 10-BIT HIGH-SPEED ADC TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution SET SAMP CLEAR SAMP SAMP ch0_dischrg ch0_samp ch1_dischrg ch1_samp eoc AD61 AD60 T SAMP DONE ADIF ADRES(0) ADRES( — Software sets ADCON. SAMP to start sampling. ...