DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet
DSPIC30F3010-20I/SP
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DSPIC30F3010-20I/SP Summary of contents
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... Rev. A2 Silicon Errata The dsPIC30F3010/3011 (Rev. A2) samples that you have received were found to conform to the specifications and functionality described in the following documents: • DS70157 – “dsPIC30F/33F Programmer’s Reference Manual” • DS70141 – “dsPIC30F3010/3011 Data Sheet” • DS70046 – “dsPIC30F Family Reference Manual” ...
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... Output Compare Module The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. 12. Quadrature Encoder Interface (QEI) Module The Index Pulse Reset mode of the QEI does not work properly when used along with count error detection ...
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... MAC class instructions not use the + = address modification not prefetch data from Y data space. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 2. Module: CPU – Instruction DAW.b The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed ...
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... Example 2 is demonstrated in Example 3. DS80389B-page 4 These instructions are identified in Table 1. Example 2 demonstrates one scenario where this occurs. Also, always use work around 2 if the C compiler is used to generate code for dsPIC30F3010/3011 devices. (2) Examples of Incorrect Operation ADDC W0, [W1++], W2 ; SUBB.b W0, [++W1 SUBBR.b W0, [++W1 ...
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... For details on the functionality of the EDT bit, see Section 2.9.2.4 “Early Termination of the DO Loop” in the “dsPIC30F Family Reference Manual” (DS70046). © 2008 Microchip Technology Inc. dsPIC30F3010/3011 6. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, the specified input frequency range of 4-10 MHz is not fully supported. ...
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... Module: Interrupt Controller – Sequential Interrupts When interrupt nesting is enabled (or NSTDIS (INTCON1<15>) bit is ‘0’), the following sequence of events will lead to an address error trap. The generic terms “Interrupt 1” and “Interrupt 2” are used to represent any two enabled dsPIC30F interrupts ...
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... When the Watchdog Timer expires, code execution will resume from the instruction immediately following the SLEEP instruction. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 10. Module: Output Compare in PWM Mode If the desired duty cycle is 0 (OCxRS = 0), the module will generate a high level glitch ...
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... Module: Quadrature Encoder Interface The Index Pulse Reset mode of the QEI does not work properly when used along with count error detection. When counting upwards, the POSCNT register will increment one extra count after the index pulse is received. The extra count will generate a false count error interrupt ...
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... Up to 153. 500 ksps Up to 256. 300 ksps Work around None. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 R Max V Temperature S DD 500Ω 4.5V to 5.5V -40°C to +85°C 5.0 kΩ 4.5V to 5.5V -40°C to +125°C 5.0 kΩ 3.0V to 5.5V -40°C to +125°C ...
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... Module: QEI Interrupt Generation The QEI module does not generate an interrupt when MAXCNT is set to 0xFFFF and the following events occur: 1. POSCNT underflows from 0x0000 to 0xFFFF. 2. POSCNT stops. 3. POSCNT overflows from 0xFFFF to 0x0000. This sequence of events occurs when the motor is running in one direction, which causes POSCNT to underflow to 0xFFFF ...
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... SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 18. Module 10-bit Addressing mode, some address matches don't set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses ...
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... Module When the I C module is configured as a slave, either in single-master or multi-master mode, the receiver buffer is filled whether a valid slave address is detected or not. Therefore receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. This overflow condition inhibits the ability to set the ...
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... PTMR will start counting PTDIR was zero. Work around None. © 2008 Microchip Technology Inc. dsPIC30F3010/3011 25. Module: Timer When the timer is being operated in Asynchronous mode using the secondary oscillator (32.768 kHz) and the device is put into Sleep mode, a clock ...
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... APPENDIX A: REVISION HISTORY Revision A (8/2008) Original version of the document. Revision B (9/2008) Updated issue 26 (PLL Lock Status Bit). DS80389B-page 14 © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...