DSPIC30F3010-20I/SP Microchip Technology, DSPIC30F3010-20I/SP Datasheet - Page 5

• Manufacturer Part Number: DSPIC30F3010-20I/SP
• Description: IC DSPIC MCU/DSP 24K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-20I/SP

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301020ISP

4. Module: PSV Operations
5. Module: Early Termination of Nested DO
EXAMPLE 4:
© 2008 Microchip Technology Inc.
LOOP1: MOV
LOOP0: MOV
Note:
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT (CORCON<11>) bit will produce unexpected
results. Specifically, the device may continue
executing code within the outer DO loop forever.
This erratum does not affect the operation of the
MPLAB C30 compiler.
Work around
The application should save the DCOUNT SFR
prior to entering the inner DO loop and restore it
upon exiting the inner DO loop. This work around is
shown in Example 4.
mode) with pre/post-decrement
.include “p30fxxxx.inc”
.......
DO
....
PUSH DCOUNT
DO
....
BTSS Flag, #0
BSET CORCON, #EDT
....
....
POP
...
For details on the functionality of the EDT bit,
see Section 2.9.2.4 “Early Termination of
the DO Loop” in the “dsPIC30F Family
Reference Manual” (DS70046).
#CNT1, LOOP0
#CNT2, LOOP1
W1, W5
DCOUNT
W5, W8
Loops
SAVE AND RESTORE
DCOUNT
;Outer loop start
;Save DCOUNT
;Inner loop
;starts
;Terminate inner
;DO-loop early
;Inner loop ends
;Restore DCOUNT
;Outer loop ends
6. Module: 4x PLL Operation
dsPIC30F3010/3011
When the 4x PLL mode of operation is selected,
the specified input frequency range of 4-10 MHz is
not fully supported.
When device V
frequency must be in the range of 4-5 MHz. When
device V
must be in the range of 4-6 MHz for both industrial
and extended temperature ranges.
Work around
1. Use 8x PLL or 16x PLL mode of operation and
2. Use the EC without PLL Clock mode with a
set final device clock speed using the
POST<1:0> oscillator postscaler control bits
(OSCCON<7:6>).
suitable clock frequency to obtain the equivalent
4x PLL clock rate.
DD
is 3.0-3.6V, the 4x PLL input frequency
DD
is 2.5-3.0V, the 4x PLL input
DS80389B-page 5