PIC24HJ64GP206-I/PT Microchip Technology, PIC24HJ64GP206-I/PT Datasheet - Page 143

• Manufacturer Part Number: PIC24HJ64GP206-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP206-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 13
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 18 Channel
• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.0
14.1
When the OCM control bits (OCxCON<2:0>) are set to
‘100’, the selected output compare channel initializes
the OCx pin to the low state and generates a single
output pulse.
To generate a single output pulse, the following steps
are required (these steps assume timer source is
initially turned off but this is not a requirement for the
module operation):
1. Determine the instruction clock cycle time. Take
2. Calculate time to the rising edge of the output pulse
3. Calculate the time to the falling edge of the pulse
4. Write the values computed in steps 2 and 3 above
5. Set Timer Period register, PRy, to value equal to or
6. Set the OCM bits to ‘100’ and the OCTSEL
7. Set the TON (TyCON<15>) bit to ‘1’, which enables
8. Upon the first match between TMRy and OCxR, the
9. When the incrementing timer, TMRy, matches the
10. To initiate another single pulse output, change the
© 2007 Microchip Technology Inc.
Note:
into account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
relative to the TMRy start value (0000h).
based on the desired pulse width and the time to the
rising edge of the pulse.
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
greater than value in OCxRS, the Output Compare
Secondary register.
(OCxCON<3>) bit to the desired timer source. The
OCx pin state will now be driven low.
the compare time base to count.
OCx pin will be driven high.
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin. No additional pulses are
driven onto the OCx pin and it remains at low. As a
result of the second compare match event, the
OCxIF interrupt flag bit is set, which will result in an
interrupt if it is enabled, by setting the OCxIE bit. For
further information on peripheral interrupts, refer to
Section 6.0 “Interrupt Controller”.
Timer and Compare register settings, if needed,
and then issue a write to set the OCM bits to ‘100’.
Disabling and re-enabling of the timer, and clear-
OUTPUT COMPARE
Setup for Single Output Pulse
Generation
This data sheet summarizes the features
of this group of PIC24HJXXXGPX06/X08/
X10 devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to the “PIC24H Family Reference
Manual”. Refer to the Microchip web site
(www.microchip.com)
PIC24H
sections.
Family
Reference
for
the
PIC24HJXXXGPX06/X08/X10
Manual
latest
The output compare module does not have to be dis-
abled after the falling edge of the output pulse. Another
pulse can be initiated by rewriting the value of the
OCxCON register.
14.2
When the OCM control bits (OCxCON<2:0>) are set to
‘101’, the selected output compare channel initializes
the OCx pin to the low state and generates output
pulses on each and every compare match event.
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required (these steps assume timer source is
initially turned off but this is not a requirement for the
module operation):
1. Determine the instruction clock cycle time. Take
2. Calculate time to the rising edge of the output pulse
3. Calculate the time to the falling edge of the pulse,
4. Write the values computed in step 2 and 3 above
5. Set Timer Period register, PRy, to value equal to or
6. Set the OCM bits to ‘101’ and the OCTSEL bit to the
7. Enable the compare time base by setting the TON
8. Upon the first match between TMRy and OCxR, the
9. When the compare time base, TMRy, matches the
10. As a result of the second compare match event, the
11. When the compare time base and the value in its
12. Steps 8 through 11 are repeated and a continuous
into account the frequency of the external clock to
the timer source (if one is used) and the timer
prescaler settings.
relative to the TMRy start value (0000h).
based on the desired pulse width and the time to the
rising edge of the pulse.
into the Output Compare register, OCxR, and the
Output Compare Secondary register, OCxRS,
respectively.
greater than value in OCxRS, the Output Compare
Secondary register.
desired timer source. The OCx pin state will now be
driven low.
(TyCON<15>) bit to ‘1’.
OCx pin will be driven high.
Output Compare Secondary register, OCxRS, the
second and trailing edge (high-to-low) of the pulse
is driven onto the OCx pin.
OCxIF interrupt flag bit set.
respective Timer Period register match, the TMRy
register resets to 0x0000 and resumes counting.
stream of pulses is generated, indefinitely. The
OCxIF flag is set on each OCxRS-TMRy compare
match event.
ing the TMRy register, are not required but may be
advantageous for defining a pulse from a known
event time boundary.
Setup for Continuous Output
Pulse Generation
DS70175F-page 141