PIC24HJ64GP206-I/PT Microchip Technology, PIC24HJ64GP206-I/PT Datasheet - Page 217

• Manufacturer Part Number: PIC24HJ64GP206-I/PT
• Description: IC PIC MCU FLASH 32KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP206-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 13
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 18 Channel
• Controller Family/series: PIC24
• No. Of I/o's: 53
• Ram Memory Size: 8KB
• Cpu Speed: 40MIPS
• No. Of Timers: 13
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.0
PIC24HJXXXGPX06/X08/X10 devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
TABLE 20-1:
© 2007 Microchip Technology Inc.
0xF80000 FBS
0xF80002 FSS
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E RESERVED3
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Note 1:
Address
Note:
programming capability
2:
SPECIAL FEATURES
Reserved bits are read as ‘1’ and must be programmed as ‘1’.
Unimplemented bits are read as ‘0’
This data sheet summarizes the features
of
of PIC24HJXXXGPX06/X08/X10 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“PIC24H
Refer
(www.microchip.com)
PIC24H
sections.
Name
DEVICE CONFIGURATION REGISTER MAP
to
Family
Family
the
FWDTEN
this
IESO
Bit 7
Microchip
FCKSM<1:0>
—
Reference
RBS<1:0>
RSS<1:0>
Reference
for
Reserved
WINDIS
Bit 6
the
—
—
web
PIC24HJXXXGPX06/X08/X10
Manual”.
Manual
(2)
group
latest
site
Bit 5
—
—
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
20.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
The device Configuration register map is shown in
Table 20-1.
The individual Configuration bit descriptions for the
FBS, FSS, FGS, FOSCSEL, FOSC, FWDT and FPOR
Configuration registers are shown in Table 20-1.
Note that address 0xF80000 is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
Bit 4
Reserved
—
—
—
—
—
—
Configuration Bits
(1)
Bit 3
—
—
—
—
BSS<2:0>
SSS<2:0>
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
Bit 2
1111’. This makes them
GSS<1:0>
FNOSC<2:0>
FPWRT<2:0>
DS70175F-page 215
Bit 1
GWRP
BWRP
SWRP
Bit 0