PIC24HJ64GP502-I/MM Microchip Technology, PIC24HJ64GP502-I/MM Datasheet - Page 104

• Manufacturer Part Number: PIC24HJ64GP502-I/MM
• Description: IC PIC MCU FLASH 64K 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ64GP502-I/MM

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-QFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24HJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel / 12 bit, 10 Channel
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 4KB
• Cpu Speed: 40MIPS
• No. Of Timers: 7
• Embedded Interface Type: CAN, I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
7.4
7.4.1
To configure an interrupt source at initialization:
1.
2.
3.
4.
7.4.2
The method used to declare an ISR and initialize the
IVT with the correct vector address depends on the
programming language (C or assembler) and the
language development tool suite used to develop the
application.
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, the program
re-enters the ISR immediately after exiting the routine.
If the ISR is coded in assembly language, it must be
terminated using a RETFIE instruction to unstack the
saved PC value, SRL value and old CPU priority level.
DS70293E-page 104
Note:
Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level
depends on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
Interrupt Setup Procedures
INITIALIZATION
INTERRUPT SERVICE ROUTINE
At a device Reset, the IPCx registers are
initialized such that all user interrupt
sources are assigned to priority level 4.
7.4.3
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.4
All user interrupts can be disabled using this
procedure:
1.
2.
To enable user interrupts, the POP instruction can be
used to restore the previous SR value.
The DISI instruction provides a convenient way to
disable interrupts of priority levels 1-6 for a fixed period
of time. Level 7 interrupt sources are not disabled by
the DISI instruction.
Note:
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
TRAP SERVICE ROUTINE
INTERRUPT DISABLE
Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
© 2011 Microchip Technology Inc.