AT91SAM7S32B-AU Atmel, AT91SAM7S32B-AU Datasheet - Page 130

IC MCU ARM7 32KB FLASH 48LQFP

AT91SAM7S32B-AU

Manufacturer Part Number
AT91SAM7S32B-AU
Description
IC MCU ARM7 32KB FLASH 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM7S32B-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Cpu Family
91S
Device Core
ARM7TDMI
Device Core Size
32b
Frequency (max)
55MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
8KB
# I/os (max)
21
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
AT91
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
21
Number Of Timers
3
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S32B-AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT91SAM7S32B-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
AT91SAM7S32B-AU-999
Manufacturer:
Atmel
Quantity:
10 000
20.2.5
20.2.5.1
130
AT91SAM7S Series Preliminary
Device Operations
Flash Read Command
Several commands on the Flash memory are available. These commands are summarized in
Table 20-3 on page
face running several read/write handshaking sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining
a read command after a write automatically flushes the load buffer in the Flash.
In the following tables, 21-6 through 21-18
This command is used to read the contents of the Flash memory. The read command can start
at any valid address in the memory plane and is optimized for consecutive reads. Read hand-
shaking can be chained; an internal address buffer is automatically increased.
Table 20-6.
Table 20-7.
Step
1
2
3
4
5
...
n
n+1
n+2
n+3
...
Step
1
2
3
4
5
6
7
...
n
• DATA[15:0] pertains to AT91SAM7S512/256/128/64/321/161
• DATA[7:0] pertains to AT91SAM7S32/16
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Read handshaking
Read handshaking
...
Write handshaking
Read Command
Read Command
126. Each command is driven by the programmer through the parallel inter-
MODE[3:0]
CMDE
ADDR0
ADDR1
DATA
DATA
...
ADDR0
ADDR1
DATA
DATA
...
MODE[3:0]
CMDE
ADDR0
ADDR1
ADDR2
ADDR3
DATA
DATA
...
ADDR0
DATA[15:0]
READ
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
READ
Memory Address LSB
Memory Address
Memory Address
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
DATA[7:0]
6175K–ATARM–30-Aug-10

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