AT91SAM7S32B-AU Atmel, AT91SAM7S32B-AU Datasheet - Page 366

• Manufacturer Part Number: AT91SAM7S32B-AU
• Description: IC MCU ARM7 32KB FLASH 48LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S32B-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: 91S
• Device Core: ARM7TDMI
• Device Core Size: 32b
• Frequency (max): 55MHz
• Interface Type: SPI/TWI/USART
• Total Internal Ram Size: 8KB
• # I/os (max): 21
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: AT91
• Maximum Speed: 55 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 21
• Number Of Timers: 3
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

31.6.3.2
366
AT91SAM7S Series Preliminary
Asynchronous Receiver
Figure 31-8. Character Transmit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter
reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready),
which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters
written in US_THR have been processed. When the current character processing is completed,
the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY raises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in
US_THR while TXRDY is low has no effect and the written character is lost.
Figure 31-9. Transmitter Status
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver over-
samples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock,
depending on the OVER bit in the Mode Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start
bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data
bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8
(OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop
bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits
as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization
mechanism only, the number of stop bits has no effect on the receiver as it considers only one
stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the
Baud Rate
TXEMPTY
Baud Rate
Example: 8-bit, Parity Enabled One Stop
US_THR
TXRDY
Clock
Write
Clock
TXD
TXD
Start
Bit
Start
Bit
D0
D1
D0
D2
D3
D1
D4
D5
D2
D6
D7
D3
Parity
Bit
Stop
Bit
D4
Start
Bit
D0
D5
D1
D2
D6
D3
D4
D7
D5
6175K–ATARM–30-Aug-10
D6
Parity
Bit
D7
Parity
Bit
Stop
Bit
Stop
Bit