DSPIC33FJ128MC202-I/MM Microchip Technology, DSPIC33FJ128MC202-I/MM Datasheet - Page 356

IC DSPIC MCU/DSP 128K 28-QFN

DSPIC33FJ128MC202-I/MM

Manufacturer Part Number
DSPIC33FJ128MC202-I/MM
Description
IC DSPIC MCU/DSP 128K 28-QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC202-I/MM

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-QFN
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
TABLE 31-17: PLL CLOCK TIMING SPECIFICATIONS (V
TABLE 31-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY
TABLE 31-19: INTERNAL RC ACCURACY
DS70291E-page 356
AC CHARACTERISTICS
OS50
OS51
OS52
OS53
Note 1:
AC CHARACTERISTICS
F21
Note 1:
AC CHARACTERISTICS
F20
Note 1:
Param
Param
Param
No.
No.
No.
2:
LPRC @ 32.768 kHz
LPRC
LPRC
F
F
T
D
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz
FRC
FRC
Symbol
PLLI
SYS
LOCK
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases
or communication clocks use this formula::
Change of LPRC frequency as V
CLK
Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.
For example: Fosc = 32 MHz, D
Characteristic
Characteristic
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
On-Chip VCO System
Frequency
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
Characteristic
(1)
SPI SCK Jitter
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
Peripheral Clock Jitter
Min
Min
-20
-30
-2
-5
(2)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
DD
CLK
changes.
Typ
= 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz.
Typ
±6
=
----------------------------- -
Min
100
0.8
0.9
-3
Max
32 MHz
------------------- -
Max
D
+20
+30
2 MHz
+2
+5
CLK
=
----------------------------------------------------------------------- -
-40°C ≤ T
-40°C ≤ T
Typ
------------------------------------------------------------- -
Peripheral Bit Rate Clock
Units
1.5
0.5
Units
DD
(1)
%
%
%
%
-40°C ≤ T
-40°C ≤ T
-40°C ≤ T
-40°C
(1)
=
= 3.0V TO 3.6V)
--------- -
3%
A
A
16
D
-40°C ≤ T
-40°C ≤ T
-40°C ≤ T
Max
F
≤ +85°C for Industrial
≤ +125°C for Extended
200
-40°C ≤ T
3.1
CLK
8
3
OSC
TA
A
A
A
=
≤ +125°C for Extended
≤ +85°C for Industrial
≤ +125°C for Extended
3%
------- -
4
+85°C for industrial
Units
MHz ECPLL, XTPLL modes
MHz
A
A
mS
A
A
%
≤ +125°C
≤ +125°C
≤ +85°C
≤ +85°C
=
© 2011 Microchip Technology Inc.
0.75%
Conditions
Conditions
Measured over 100 ms
period
Conditions
V
V
V
V
DD
DD
DD
DD
= 3.0-3.6V
= 3.0-3.6V
= 3.0-3.6V
= 3.0-3.6V

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