DSPIC33FJ128MC202-I/MM Microchip Technology, DSPIC33FJ128MC202-I/MM Datasheet - Page 429

• Manufacturer Part Number: DSPIC33FJ128MC202-I/MM
• Description: IC DSPIC MCU/DSP 128K 28-QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC202-I/MM

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 28-QFN
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Motor Control PWM .......................................................... 209
Motor Control PWM Module
MPLAB ASM30 Assembler, Linker, Librarian ................... 340
MPLAB Integrated Development Environment Software .. 339
MPLAB PM3 Device Programmer .................................... 342
MPLAB REAL ICE In-Circuit Emulator System................. 341
MPLINK Object Linker/MPLIB Object Librarian ................ 340
N
NVM Module
O
Open-Drain Configuration ................................................. 164
Output Compare ............................................................... 205
P
Packaging ......................................................................... 399
Peripheral Module Disable (PMD) .................................... 158
Pinout I/O Descriptions (table) ............................................ 17
PMD Module
PORTA
PORTB
Power-on Reset (POR) ....................................................... 88
Power-Saving Features .................................................... 157
Program Address Space ..................................................... 39
Program Memory
Q
Quadrature Encoder Interface (QEI) ................................. 223
Quadrature Encoder Interface (QEI) Module
R
Reader Response ............................................................. 424
Register Map
Registers
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Start and End Address................................................ 69
W Address Register Selection .................................... 69
2-Output Register Map................................................ 52
6-Output Register Map................................................ 51
Register Map............................................................... 66
Details ....................................................................... 400
Marking ..................................................................... 399
Register Map............................................................... 66
Register Map......................................................... 64, 65
Register Map............................................................... 65
Clock Frequency and Switching................................ 157
Construction................................................................ 72
Data Access from Program Memory Using Program
Data Access from Program Memory Using Table Instruc-
Data Access from, Address Generation...................... 73
Memory Map ............................................................... 39
Table Read Instructions
Visibility Operation ...................................................... 75
Interrupt Vector ........................................................... 40
Organization................................................................ 40
Reset Vector ............................................................... 40
Register Map............................................................... 52
CRC ............................................................................ 64
Dual Comparator......................................................... 64
Parallel Master/Slave Port .......................................... 63
Real-Time Clock and Calendar................................... 64
AD1CHS0 (ADC1 Input Channel 0 Select ................ 284
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 282
AD1CON1 (ADC1 Control 1) .................................... 277
Space Visibility.................................................... 75
tions .................................................................... 74
TBLRDH ............................................................. 74
TBLRDL .............................................................. 74
AD1CON2 (ADC1 Control 2) .................................... 279
AD1CON3 (ADC1 Control 3) .................................... 280
AD1CON4 (ADC1 Control 4) .................................... 281
AD1CSSL (ADC1 Input Scan Select Low) ............... 286
AD1PCFGL (ADC1 Port Configuration Low) ............ 286
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 259
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 260
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 260
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 261
CiCFG1 (ECAN Baud Rate Configuration 1)............ 257
CiCFG2 (ECAN Baud Rate Configuration 2)............ 258
CiCTRL1 (ECAN Control 1)...................................... 250
CiCTRL2 (ECAN Control 2)...................................... 251
CiEC (ECAN Transmit/Receive Error Count) ........... 257
CiFCTRL (ECAN FIFO Control) ............................... 253
CiFEN1 (ECAN Acceptance Filter Enable)............... 259
CiFIFO (ECAN FIFO Status) .................................... 254
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 263,
CiINTE (ECAN Interrupt Enable) .............................. 256
CiINTF (ECAN Interrupt Flag) .................................. 255
CiRXFnEID (ECAN Acceptance Filter n Extended Identi-
CiRXFnSID (ECAN Acceptance Filter n Standard Identi-
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 266
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 266
CiRXMnEID (ECAN Acceptance Filter Mask n Extended
CiRXMnSID (ECAN Acceptance Filter Mask n Standard
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 267
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 267
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 269,
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 268
CiVEC (ECAN Interrupt Code) ................................. 252
CLKDIV (Clock Divisor) ............................................ 151
CORCON (Core Control)...................................... 31, 96
DFLTCON (QEI Control) .......................................... 226
DMACS0 (DMA Controller Status 0) ........................ 140
DMACS1 (DMA Controller Status 1) ........................ 142
DMAxCNT (DMA Channel x Transfer Count)........... 139
DMAxCON (DMA Channel x Control)....................... 136
DMAxPAD (DMA Channel x Peripheral Address) .... 139
DMAxREQ (DMA Channel x IRQ Select) ................. 137
DMAxSTA (DMA Channel x RAM Start Address A) . 138
DMAxSTB (DMA Channel x RAM Start Address B) . 138
DSADR (Most Recent DMA RAM Address) ............. 143
I2CxCON (I2Cx Control)........................................... 235
I2CxMSK (I2Cx Slave Mode Address Mask)............ 239
I2CxSTAT (I2Cx Status) ........................................... 237
IFS0 (Interrupt Flag Status 0) ........................... 100, 107
IFS1 (Interrupt Flag Status 1) ........................... 102, 109
IFS2 (Interrupt Flag Status 2) ........................... 104, 111
IFS3 (Interrupt Flag Status 3) ........................... 105, 112
IFS4 (Interrupt Flag Status 4) ........................... 106, 113
INTCON1 (Interrupt Control 1) ................................... 97
INTCON2 (Interrupt Control 2) ................................... 99
INTTREG Interrupt Control and Status Register ...... 131
IPC0 (Interrupt Priority Control 0) ............................. 114
IPC1 (Interrupt Priority Control 1) ............................. 115
IPC11 (Interrupt Priority Control 11) ......................... 124
IPC14 (Interrupt Priority Control 14) ......................... 125
IPC15 (Interrupt Priority Control 15) ......................... 126
IPC16 (Interrupt Priority Control 16) ......................... 127
IPC17 (Interrupt Priority Control 17) ......................... 128
IPC18 (Interrupt Priority Control 18) ................. 129, 130
264
fier) ................................................................... 263
fier) ................................................................... 262
Identifier) .......................................................... 265
Identifier) .......................................................... 265
270, 272
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