AT89C5130A-PUTUM Atmel, AT89C5130A-PUTUM Datasheet - Page 100

• Manufacturer Part Number: AT89C5130A-PUTUM
• Description: IC 8051 MCU FLASH 16K USB 32QFN
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5130A-PUTUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32QFN EP
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART/USB
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 1.25 KB
• Maximum Clock Frequency: 48 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C5130A-PUTIM; AT89C5130A-PUTIM

19.3.5.2
100
AT89C5130A/31A-M
Serial Peripheral Status Register (SPSTA)
Reset Value = 0001 0100b
Not bit addressable
The Serial Peripheral Status Register contains flags to signal the following conditions:
Table 19-4
Table 19-4.
SPSTA - Serial Peripheral Status and Control register (0C4H)
Bit Number
Number
• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error)
Bit
SPIF
2
1
0
7
6
5
7
describes the SPSTA register and explains the use of every bit in the register.
Bit Mnemonic
Mnemonic
SSERR
SPSTA Register
WCOL
WCOL
CPHA
SPR1
SPR0
SPIF
Bit
6
Description
Serial Peripheral data transfer flag
Cleared by hardware to indicate data transfer is in progress or has been approved by a
clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
Write Collision flag
Cleared by hardware to indicate that no collision has occurred or has been approved by a
clearing sequence.
Set by hardware to indicate that a collision has been detected.
Synchronous Serial Slave Error flag
Set by hardware when SS is de-
asserted before the end of a received data.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
Description
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see CPOL).
SPR2 SPR1 SPR0 Serial Peripheral Rate
000Reserved
00 1F
010 F
011F
100F
10 1F
110F
1 11Reserved
SSERR
5
CLK PERIPH/
CLK PERIPH/
CLK PERIPH/
CLK PERIPH/
CLK PERIPH/
CLK PERIPH/
16
32
128
4
8
64
MODF
4
3
-
2
-
1
-
4337K–USB–04/08
0
-