AT89C5130A-PUTUM Atmel, AT89C5130A-PUTUM Datasheet - Page 131

• Manufacturer Part Number: AT89C5130A-PUTUM
• Description: IC 8051 MCU FLASH 16K USB 32QFN
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5130A-PUTUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32QFN EP
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART/USB
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 1.25 KB
• Maximum Clock Frequency: 48 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C5130A-PUTIM; AT89C5130A-PUTIM

21.6
21.6.1
21.6.2
4337K–USB–04/08
Isochronous Transactions
Isochronous OUT Transactions in Standard Mode
Isochronous OUT Transactions in Ping-pong Mode
An endpoint will be first enabled and configured before being able to receive Isochronous
packets.
When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller.
This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint,
store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If the
received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register values
are equal to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in
FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUTB0 bit to
allow the USB controller to store the next OUT packet data into the endpoint FIFO. Until the
RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at each OUT transac-
tion will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will store only
the remaining bytes into the FIFO.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be
stored, but the USB controller will consider that the packet is valid if the CRC is correct.
An endpoint will be first enabled and configured before being able to receive Isochronous
packets.
When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the USB
controller. This triggers an interrupt if enabled. The firmware has to select the corresponding
endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers. If
the received packet is a ZLP (Zero Length Packet), the UBYCTLX and UBYCTHX register val-
ues are equal to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet stored in
FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUB0 bit to
allow the USB controller to store the next OUT packet data into the endpoint FIFO bank 0. This
action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has been cleared by the firm-
ware, the data sent by the Host on the bank 0 endpoint FIFO will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the USB
controller will store only the remaining bytes into the FIFO.
When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware empties the bank 1 endpoint
FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been cleared by the firm-
ware, the data sent by the Host on the bank 1 endpoint FIFO will be lost.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each new
packet receipt.
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