AT89C5130A-PUTUM Atmel, AT89C5130A-PUTUM Datasheet - Page 15

• Manufacturer Part Number: AT89C5130A-PUTUM
• Description: IC 8051 MCU FLASH 16K USB 32QFN
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5130A-PUTUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32QFN EP
• Device Core: 8051
• Family Name: 89C
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: SPI/TWI/UART/USB
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 1.25 KB
• Maximum Clock Frequency: 48 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: AT89C5130A-PUTIM; AT89C5130A-PUTIM

5.3
5.3.1
Figure 5-3.
4337K–USB–04/08
PLL
PLL Description
CLOCK
OSC
PLL Block Diagram and Symbol
N divider
In order to optimize the power consumption, the oscillator inverter is inactive when the PLL out-
put is not selected for the USB device.
Figure 5-2.
The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the USB Clock)
synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to
generate the USB interface clock. Figure 5-3 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the
comparison between the reference clock coming from the N divider and the reverse clock com-
ing from the R divider and generates some pulses on the Up or Down signal depending on the
edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the
clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 5-3) is
set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by inject-
ing or extracting charges from the external filter connected on PLLF pin (see Figure 5-4). Value
of the filter components are detailed in the Section “DC Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage V
the charge pump. It generates a square wave signal: the PLL clock.
N3:0
Crystal Connection
PLLCON.1
PLLCON.0
PLOCK
PLLEN
USBclk
PFLD
Down
=
Up
OSCclk
---------------------------------------------- -
R divider
VSS
R3:0
PLLF
CHP
N
+
×
1
(
C1
C2
R
+
Vref
1
)
Q
VCO
X1
X2
AT89C5130A/31A-M
USB Clock Symbol
USB Clock
CLOCK
USB
REF
produced by
15