DSPIC33FJ32GS610-I/PT Microchip Technology, DSPIC33FJ32GS610-I/PT Datasheet - Page 404

• Manufacturer Part Number: DSPIC33FJ32GS610-I/PT
• Description: IC MCU/DSP 32KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GS610-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 32KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
APPENDIX B:
Revision A (March 2009)
This is the initial release of this document.
TABLE B-1:
DS70591C-page 404
“High-Performance, 16-Bit Digital
Signal Controllers”
Section 4.0 “Memory Organization”
Section Name
MAJOR SECTION UPDATES
REVISION HISTORY
Added “DMA Channels” column and updated the RAM size to 9K for the
dsPIC33FJ64GS406 devices in the controller families table (see Table 1).
Updated the pin diagrams as follows:
• 64-pin TQFP and QFN
• 80-pin TQFP
• 100-pin TQFP
Added Data Memory Map for Devices with 8 KB RAM (see Figure 4-4).
Removed SFRs IPC25 and IPC26 from the Interrupt Controller Register
Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices (see
Table 4-7).
The following bits in the Interrupt Controller Register Map for
dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices were changed to
unimplemented (see Table 4-7):
• Bit 2 of IFS1
• Bits 9-7 of IFS6
• Bit 2 of IEC1
• Bits 9-7 of IEC6
• Bits 10-8 of IPC4
Removed OSCTUN2 and LFSR, updated OSCCON and OSCTUN,
renamed bit 13 of the REFOCON SFR in the System Control Register
Map from ROSIDL to ROSSLP and changed the All Resets value from
‘0000’ to ‘2300’ for the ACLKCON SFR (see Table 4-56).
Updated bit 1 of the PMD Register Map for dsPIC33FJ64GS608 devices
from unimplemented to C1MD (see Table 4-60).
- Removed FLT8 from pin 51
- Added FLT8 to pin 60
- Added FLT17 to pin 31
- Added FLT18 to pin32
- Removed FLT8 from pin 63
- Added FLT8 to pin 76
- Added FLT19 to pin 53
- Added FLT20 to pin 52
- Removed FLT8 from pin 78
- Added FLT8 to pin 93
- Added SYNCO1 to pin 95
Preliminary
Revision B (November 2009)
The revision includes the following global update:
• Added Note 2 to the shaded table that appears at
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in Table B-1.
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
Update Description
 2010 Microchip Technology Inc.