DSPIC33FJ128GP708-I/PT

Manufacturer Part NumberDSPIC33FJ128GP708-I/PT
DescriptionIC DSPIC MCU/DSP 128K 80TQFP
ManufacturerMicrochip Technology
SeriesdsPIC™ 33F
DSPIC33FJ128GP708-I/PT datasheets
 


Specifications of DSPIC33FJ128GP708-I/PT

Program Memory TypeFLASHProgram Memory Size128KB (128K x 8)
Package / Case80-TFQFPCore ProcessordsPIC
Core Size16-BitSpeed40 MIPs
ConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USARTPeripheralsAC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o69Ram Size16K x 8
Voltage - Supply (vcc/vdd)3 V ~ 3.6 VData ConvertersA/D 24x10b/12b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
ProductDSCsData Bus Width16 bit
Processor SeriesDSPIC33FCoredsPIC
Maximum Clock Frequency40 MHzNumber Of Programmable I/os69
Data Ram Size16 KBMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development Tools52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By SupplierPG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033Minimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
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4.0
DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer)
and buffers or variables stored in RAM with minimal
CPU
intervention.
The
DMA
automatically copy entire blocks of data, without the
user software having to read or write peripheral Special
Function Registers (SFRs) every time a peripheral
interrupt occurs. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM space.
The DMA Controller features eight identical data
transfer channels, each with its own set of control and
status registers. The UART, SPI, DCI, Input Capture,
Output Compare, ECAN™ and A/D modules can utilize
DMA. Each DMA channel can be configured to copy
data either from buffers stored in DMA RAM to
peripheral SFRs or from peripheral SFRs to buffers in
DMA RAM.
Each channel supports the following features:
• Word or byte-sized data transfers
• Transfers from peripheral to DMA RAM or DMA
RAM to peripheral
FIGURE 4-1:
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
DMA RAM
SRAM
PORT 1
PORT 2
SRAM X-Bus
CPU Peripheral DS Bus
Non-DMA
CPU
Ready
Peripheral
Note: CPU and DMA address buses are not shown for clarity.
© 2005 Microchip Technology Inc.
• Indirect addressing of DMA RAM locations with or
without automatic post-increment
• Peripheral Indirect Addressing – In some
peripherals, the DMA RAM read/write addresses
may be partially derived from the peripheral
• One-Shot Block Transfers – Terminating DMA
Controller
can
transfer after one block transfer
• Continuous Block Transfers – Reloading DMA
RAM buffer start address after every block
transfer is complete
• Ping-Pong Mode – Switching between two DMA
RAM start addresses between successive block
transfers, thereby filling two buffers alternately
• Automatic or manual initiation of block transfers
• Each channel can select from 32 possible
sources of data sources or destinations
For each DMA channel, a DMA interrupt request is
generated when a block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled. Additionally, a DMA error trap
is generated in either of the following Fault conditions:
• DMA RAM data write collision between the CPU
and a peripheral
• Peripheral SFR data write collision between the
CPU and the DMA Controller
Peripheral Indirect Address
DMA Controller
DMA
Channels
DMA DS Bus
Preliminary
dsPIC33F
DMA
Ready
Peripheral 3
CPU
DMA
CPU
DMA
CPU
DMA
DMA
DMA
Ready
Ready
Peripheral 2
Peripheral 1
DS70155C-page 15