DSPIC33FJ128GP708-I/PT Microchip Technology, DSPIC33FJ128GP708-I/PT Datasheet - Page 20

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DSPIC33FJ128GP708-I/PT

Manufacturer Part Number
DSPIC33FJ128GP708-I/PT
Description
IC DSPIC MCU/DSP 128K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
69
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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dsPIC33F
5.1
Each interrupt source can be user-assigned to one of
8 priority levels, 0 through 7. Levels 7 and 1 represent
the
respectively. A priority level of 0 disables the interrupt.
Since more than one interrupt request source may be
assigned to a user-specified priority level, a means is
provided to assign priority within a given level. This
method is called “Natural Order Priority”.
The Natural Order Priority of an interrupt is numerically
identical to its vector number. The Natural Order
Priority scheme has 0 as the highest priority and 74 as
the lowest priority.
The ability for the user to assign every interrupt to one
of eight priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low Natural Order Priority, thereby providing much
flexibility in designing applications that use a large
number of peripherals.
5.2
Interrupts, by default, are nestable. Any ISR that is in
progress may be interrupted by another source of
interrupt with a higher user-assigned priority level.
Interrupt nesting may be optionally disabled by
setting the NSTDIS control bit (INTCON1<15>).
When the NSTDIS control bit is set, all interrupts in
progress will force the CPU priority to level 7 by
setting IPL<2:0> = 111. This action will effectively
mask all other sources of interrupt until a RETFIE
instruction is executed. When interrupt nesting is
disabled, the user-assigned interrupt priority levels
will have no effect, except to resolve conflicts
between simultaneous pending interrupts.
The IPL<2:0> bits become read-only when interrupt
nesting is disabled. This prevents the user software
from setting IPL<2:0> to a lower value, which would
effectively re-enable interrupt nesting.
TABLE 5-2:
DS70155C-page 18
highest
Vector Number
Interrupt Priority
Interrupt Nesting
0
1
2
3
4
5
6
7
and
TRAP VECTORS
lowest
maskable
IVT Address
0x00000C
0x000006
0x000008
0x00000A
0x00000E
0x000010
0x000012
0x000004
priorities,
Preliminary
5.3
Traps can be considered as non-maskable, nestable
interrupts that adhere to a fixed priority structure.
Traps are intended to provide the user a means to
correct erroneous operation during debug and when
operating within the application. If the user does not
intend to take corrective action in the event of a trap
error condition, these vectors must be loaded with the
address of a software routine that will reset the device.
Otherwise, the trap vector is programmed with the
address of a service routine that will correct the trap
condition.
The dsPIC33F has four implemented sources of
non-maskable traps:
• Oscillator Failure Trap
• Address Error Trap
• Stack Error Trap
• Math Error Trap
• DMA Trap
Many of these trap conditions can only be detected
when they happen. Consequently, the instruction that
caused the trap is allowed to complete before
exception processing begins. Therefore, the user may
have to correct the action of the instruction that
caused the trap.
Each trap source has a fixed priority as defined by its
position in the IVT. An oscillator failure trap has the
highest priority, while an arithmetic error trap has the
lowest priority.
Table 5-2 contains information about the trap vector.
5.4
Any available interrupt can be manually generated by
user software (even if the corresponding peripheral is
disabled), simply by enabling the interrupt and then
setting the interrupt flag bit when required.
AIVT Address
0x00008A
0x00008C
0x00008E
0x000084
0x000086
0x000088
0x000090
0x000092
Traps
Generating a Software Interrupt
© 2005 Microchip Technology Inc.
Reserved
Oscillator Failure
Address Error
Stack Error
Math Error
DMA Error Trap
Reserved
Reserved
Trap Source

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