PIC16LF877-04/L Microchip Technology, PIC16LF877-04/L Datasheet - Page 98

IC MCU FLASH 8KX14 EE A/D 44PLCC

PIC16LF877-04/L

Manufacturer Part Number
PIC16LF877-04/L
Description
IC MCU FLASH 8KX14 EE A/D 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet

Specifications of PIC16LF877-04/L

Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Controller Family/series
PIC16LF
No. Of I/o's
33
Eeprom Memory Size
256Byte
Ram Memory Size
368Byte
Cpu Speed
4MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16LF877-04/L
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC16F87X
REGISTER 10-2:
DS30292C-page 96
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Don’t care
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and load of the receive buffer when
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
Legend:
R = Readable bit
- n = Value at POR
OERR: Overrun Error bit
RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware)
R/W-0
SPEN
RSR<8> is set
R/W-0
RX9
R/W-0
SREN
W = Writable bit
’1’ = Bit is set
R/W-0
CREN
ADDEN
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
FERR
R-0
2001 Microchip Technology Inc.
x = Bit is unknown
OERR
R-0
RX9D
R-x
bit 0

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