AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 288

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.4
28.4.1
28.4.1.1
288
Arbitration
AT91SAM9R64/RL64 Preliminary
Arbitration rules
Undefined Length Burst Arbitration
FIXED_DEFMSTR field allows to choose a fixed default master provided that DEFMSTR_TYPE
is set to fixed default master. Please refer to the Bus Matrix user interface description.
The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict
cases occur, basically when two or more masters try to access the same slave at the same time.
One arbiter per AHB slave is provided, allowing to arbitrate each slave differently.
The Bus Matrix provides to the user the possibility to choose between 2 arbitration types, and
this for each slave:
This choice is given through the field ARBT of the Slave Configuration Registers
(MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each
slave.
When a re-arbitration has to be done, it is realized only under some specific conditions detailed
in the following paragraph.
Each arbiter has the ability to arbitrate between two or more different master’s requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra-
tion may only take place during the following cycles:
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix
provides specific logic in order to re-arbitrate before the end of the INCR transfer.
A predicted end of burst is used as for defined length burst transfer, which is selected between
the following:
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
1. Idle Cycles: when a slave is not connected to any master or is connected to a master
2. Single Cycles: when a slave is currently doing a single access.
3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For
4. Slot Cycle Limit: when the slot cycle counter has reach the limit value indicating that the
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will
2. Four beat bursts: predicted end of burst is generated at the end of each four beat
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat
which is not currently accessing it.
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst (See “Undefined Length Burst Arbitration” on
page iv.).
current master access is too long and must be broken (See “Slot Cycle Limit Arbitra-
tion” on page iv.).
never be broken.
boundary inside INCR transfer.
boundary inside INCR transfer.
boundary inside INCR transfer.
6289C–ATARM–28-May-09