AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 50

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.2
Figure 12-1. ARM926EJ-S Internal Functional Block Diagram
12.3
12.3.1
12.3.2
50
Block Diagram
ARM9EJ-S Processor
AT91SAM9R64/RL64 Preliminary
ARM9EJ-S Operating States
Switching State
Interface
ICE
EmbeddedICE
WDATA
-RT
Interface
ARM9EJ-S
ETM
The ARM9EJ-S processor can operate in three different states, each with a specific instruction
set:
In Jazelle state, all instruction Fetches are in words.
The operating state of the ARM9EJ-S core can be switched between:
• ARM state: 32-bit, word-aligned ARM instructions.
• THUMB state: 16-bit, halfword-aligned Thumb instructions.
• Jazelle state: variable length, byte-aligned Jazelle instructions.
• ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
Processor
RDATA
INSTR
Coprocessor
DA
Interface
IA
Droute
Iroute
ARM926EJ-S
DCACHE
DEXT
MMU
ICACHE
IEXT
Interface
Interface
TCM
Instruction
Bus
Unit
Interface
Interface
AHB
Data
AHB
6289C–ATARM–28-May-09
AHB
AHB