AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 743

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.4.8.6
6289C–ATARM–28-May-09
Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)
A simple algorithm can be used by the application to send packets regardless of the number of
banks associated to the endpoint.
Algorithm Description for Each Packet:
The application is notified that it is possible to write a new packet to the DPR by the
TX_PK_RDY interrupt. This interrupt can be enabled or masked by setting the TX_PK_RDY bit
in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.
Algorithm Description to Fill Several Packets:
Using the previous algorithm, the application is interrupted for each packet. It is possible to
reduce the application overhead by writing linearly several banks at the same time. The
AUTO_VALID bit in the UDPHS_EPTCTLx must be set by writing the AUTO_VALID bit in the
UDPHS_EPTCTLENBx register.
The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the interven-
tion of the CPU. This means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit)
is done by hardware.
The application is notified that all banks are free, so that it is possible to write another burst of
packets by the BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the
BUSY_BANK flag in the UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.
This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism
does not operate.
A Z e r o L e n g t h P a c k e t c a n b e s e n t b y s e t t i n g j u s t t h e T X _ P K T R D Y f l a g i n t h e
UDPHS_EPTSETSTAx register.
The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buf-
fer from the memory to the DPR or from the DPR to the processor memory under the UDPHS
control. The DMA can be used for all transfer types except control transfer.
Example DMA configuration:
• The application waits for TX_PK_RDY flag to be cleared in the UDPHS_EPTSTAx register
• The application writes one USB packet of data in the DPR through the
• The application sets TX_PK_RDY flag in the UDPHS_EPTSETSTAx register.
• The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The
• The application writes a number of bytes inferior to the number of free DPR banks for the
• If the last packet is incomplete (i.e., the last byte of the bank has not been written) the
1. Program UDPHS_DMAADDRESS x with the address of the buffer that should be
2. Enable the interrupt of the DMA in UDPHS_IEN
3. Program UDPHS_ DMACONTROLx:
before it can perform a write access to the DPR.
memory window.
application must wait that at least one bank is free.
endpoint. Each time the application writes the last byte of a bank, the TX_PK_RDY signal is
automatically set by the UDPHS.
application must set the TX_PK_RDY bit in the UDPHS_EPTSETSTAx register.
transferred.
AT91SAM9R64/RL64 Preliminary
64
KB endpoint logical
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