AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 787
AT91SAM9R64-CU
Manufacturer Part Number
AT91SAM9R64-CU
Description
MCU ARM9 64K SRAM 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9R64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 3 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
49
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
144LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9R64-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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41.5.19
Name:
Access Type:
• EPT_ENABL: Endpoint Enable
0 = If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a
hardware or UDPHS bus reset and participate in the device configuration.
1 = If set, the endpoint is enabled according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.
• INTDIS_DMA: Interrupt Disables DMA
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the
UDPHS_IEN register EPT_INT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source
or clear this bit if transfer completion is needed.
If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally
completed, but the new DMA packet transfer is not started (not requested).
6289C–ATARM–28-May-09
SHRT_PCKT
MDATA_RX
NAK_OUT
For IN Transfer:
If this bit is set, then the UDPHS_EPTSTAx register TX_PK_RDY bit is set automatically when the current bank is full
and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.
The user may still set the UDPHS_EPTSTAx register TX_PK_RDY bit if the current bank is not full, unless the user
wants to send a Zero Length Packet by software.
For OUT Transfer:
If this bit is set, then the UDPHS_EPTSTAx register RX_BK_RDY bit is automatically reset for the current bank when
the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx
register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is
reached.
The user may still clear the UDPHS_EPTSTAx register RX_BK_RDY bit, for example, after completing a DMA buffer
by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the
remaining data bank(s).
31
23
15
–
7
UDPHS Endpoint Control Register
ERR_FLUSH
DATAX_RX
NAK_IN/
30
22
14
Read-only
–
–
6
UDPHS_EPTCTLx [x=0..6]
ERR_CRISO/
ERR_NBTRA
STALL_SNT/
29
21
13
–
–
5
–
ERR_FL_ISO
RX_SETUP/
NYET_DIS
28
20
12
–
–
4
AT91SAM9R64/RL64 Preliminary
TX_PK_RDY/
ERR_TRANS
INTDIS_DMA
27
19
11
–
–
3
BUSY_BANK
TX_COMPLT
26
18
10
–
2
–
AUTO_VALID
RX_BK_RDY
25
17
–
–
9
1
ERR_OVFLW
EPT_ENABL
24
16
–
–
8
0
787
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