AT91SAM9R64-CU Atmel, AT91SAM9R64-CU Datasheet - Page 711

• Manufacturer Part Number: AT91SAM9R64-CU
• Description: MCU ARM9 64K SRAM 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9R64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 49
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 144LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

40.6.2
Figure 40-4. Logical Channel Assignment
6289C–ATARM–28-May-09
(Controller Output)
(Codec output)
AC‘97 Controller Channel Organization
AC97RX
AC97FS
AC97TX
Slot #
AC97C_ICA = 0x0000_0009
AC97C_OCA = 0x0000_0209
TAG
TAG
0
The AC’97 Controller features a Codec channel and 2 logical channels; Channel A and Channel
B.
The Codec channel controls AC‘97 Codec registers, it enables write and read configuration val-
ues in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot
1 and slot 2 exclusively, in both input and output directions.
Channel A and Channel B transfer data to/from AC97 codec. All audio samples and modem
data must transit by these two channels. However, Channel A is connected to PDC channels
thus making it suitable for audio streaming applications.
Each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by
either Channel A or Channel B. The slot to channel assignment is configured by two registers:
The AC’97 Controller Input Channel Assignment Register (AC97C_ICA) configures the input slot
to channel assignment. The AC’97 Controller Output Channel Assignment Register
(AC97C_OCA) configures the output slot to channel assignment.
A slot can be left unassigned to a channel by the AC’97 Controller. Slots 0, 1,and 2 cannot be
assigned to Channel A or to Channel B through the AC97C_OCA and AC97C_ICA Registers.
The width of sample data, that transit via Channel A and Channel B varies and can take one of
these values; 10, 16, 18 or 20 bits.
STATUS
• AC’97 Controller Input Channel Assignment Register (AC97C_ICA)
• AC’97 Controller Output Channel Assignment Register (AC97C_OCA)
ADDR
ADDR
CMD
Codec Channel
1
Codec Channel
STATUS
DATA
DATA
CMD
2
3
L Front
LEFT
PCM
PCM
Channel A
Channel A
R Front
RIGHT
4
PCM
PCM
LINE 1
LINE 1
AT91SAM9R64/RL64 Preliminary
5
DAC
DAC
6
Center
PCM
PCM
MIC
L SURR
RSVED
7
PCM
R SURR
RSVED
PCM
8
RSVED
PCM
9
LFE
LINE 2
LINE 2
10
ADC
DAC
11
HSET
HSET
ADC
DAC
STATUS
12
CTRL
IO
IO
711