AT91SAM9XE128-QU Atmel, AT91SAM9XE128-QU Datasheet
AT91SAM9XE128-QU
Specifications of AT91SAM9XE128-QU
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AT91SAM9XE128-QU Summary of contents
Page 1
... One 32-Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32-Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16-Kbyte (for AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed – 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024 Pages of 512 Bytes Respectively. ...
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... High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2 • Two Two-wire Interfaces (TWI) – Master, Multi-master and Slave Mode Operation – General Call Supported in Slave Mode – Connection to PDC Channel to Optimize Data Transfers in Master Mode Only AT91SAM9XE128/256/512 Preliminary 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding ...
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... Built-in lock bits a security bit and MMU protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM9XE128/256/512 embeds an Ethernet MAC, one USB Device Port, and a USB Host Controller. It also integrates several standard peripherals, like six UARTs, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and a MultiMedia/SD Card Interface ...
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... AT91SAM9XE128/256/512 Block Diagram The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in on PIO Controller A” on page PIO Controller C” on page defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package. ...
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... Figure 2-1. AT91SAM9XE128/256/512 Block Diagram 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Filter 5 ...
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... TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select JTAGSEL JTAG Selection RTCK Return Test Clock AT91SAM9XE128/256/512 Preliminary 6 gives details on the signal name classified by peripheral. Active Type Level Power Supplies Power Power Power Power Power Power ...
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... External Wait Signal NCS0 - NCS7 Chip Select Lines NWR0 - NWR3 Write Signal NRD Read Signal NWE Write Enable NBS0 - NBS3 Byte Mask Signal 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Active Type Level Flash Memory Input High Reset/Test I/O Low Input Debug Unit - DBGU ...
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... RTSx USARTx Request To Send CTSx USARTx Clear To Send DTR0 USART0 Data Terminal Ready DSR0 USART0 Data Set Ready DCD0 USART0 Data Carrier Detect RI0 USART0 Ring Indicator AT91SAM9XE128/256/512 Preliminary 8 Active Reference Type Level CompactFlash Support Output Low VDDIOM Output Low VDDIOM ...
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... USB Host Port A Data - HDPB USB Host Port B Data + HDMB USB Host Port B Data + DDM USB Device Port Data - DDP USB Device Port Data + 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Active Type Level Synchronous Serial Controller - SSC Output Input I/O I/O I/O ...
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... I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter- face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. 2. Refer to PIO Multiplexing (see AT91SAM9XE128/256/512 Preliminary 10 Active Type ...
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... Package and Pinout The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch 217-ball LFBGA Green package (0.8 mm ball pitch). 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character- istics” of the product datasheet. ...
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... GNDBU 96 45 XOUT32 97 46 XIN32 98 47 VDDBU 99 48 WKUP 100 49 SHDN 101 50 HDMA 102 51 HDPA 103 52 VDDIOP0 104 AT91SAM9XE128/256/512 Preliminary 12 Signal Name Pin Signal Name GND 105 RAS DDM 106 D0 DDP 107 D1 PC13 108 D2 PC11 109 D3 PC10 110 D4 PC14 111 D5 PC9 ...
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... LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Character- istics” of the product datasheet. Figure 4-2. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary shows the orientation of the 217-ball LFBGA package. 217-ball LFBGA Package Outline (Top View ...
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... H15 C13 DDP H16 C14 HDMB H17 C15 NC J1 C16 VDDIOP0 J2 C17 SHDN RAS J10 AT91SAM9XE128/256/512 Preliminary 14 Signal Name Pin Signal Name A5 J14 TDO GND J15 PB19 A10 J16 TDI GND J17 PB16 VDDCORE K1 PC24 GND K2 PC20 VDDIOM K3 D15 GND K4 PC21 ...
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... Power Considerations 5.1 Power Supplies The AT91SAM9XE128/256/512 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1 ...
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... Separate Masters for both instruction and data access providing complete Matrix – Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit AT91SAM9XE128/256/512 Preliminary 16 each quarter of the page ...
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... Allows Handling of Dynamic Exception Vectors 7.2.1 Matrix Masters The Bus Matrix of the AT91SAM9XE128/256/512 manages six Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (Low to High priorities): – TWI0 Transmit Channel – TWI1 Transmit Channel – DBGU Transmit Channel – USART4 Transmit Channel – USART3 Transmit Channel AT91SAM9XE128/256/512 Preliminary 18 List of Bus Matrix Slaves (Continued) Internal Flash Internal Peripherals Reserved 0 and 1 ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 19 ...
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... Memories Figure 8-1. AT91SAM9XE128/256/512 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes ...
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... The embedded ROM contains the Fast Flash Programming and the SAM-BA boot programs. Each of these two programs is stored on 16-Kbyte Boundary of FFPI and the program executed 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Table 8-3, “Internal Memory Mapping,” on page 25 Figure 8-1 on page for details. ...
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... Boot Assistant The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. AT91SAM9XE128/256/512 Preliminary 22 0x0000 0000 SAM-BA Program ...
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... The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). 8.1.5 Embedded Flash The Flash of the AT91SAM9XE128/256/512 is organized in 256/512/1024 pages of 512 bytes directly connected to the 32-bit internal bus. Each page contains 128 words. The Flash contains a 512-byte write buffer allowing the programming of a page. This buffer is write-only as 128 32-bit words, and accessible all along the 1-Mbyte address space, so that each word can be written at its final address ...
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... FFFF or 0x0023 FFFF or 0x0027 FFFF 8.1.5.3 GPNVM Bits The AT91SAM9XE128/256/512 features four GPNVM bits that can be cleared or set respec- tively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. Table 8-2. GPNVMBit[#] 8.1.5.4 ...
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... Auto baudrate detection • SAM-BA Boot in case no valid program is detected in external NVM, supporting – Serial communication on a DBGU – USB Device Port 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary summarizes the Internal Memory Mapping for each Master, depending on the Remap Internal Memory Mapping REMAP = 0 Address ...
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... Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported AT91SAM9XE128/256/512 Preliminary 26 Figure 8-1 on page 20. 6254C–ATARM–22-Jan-10 ...
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... The purpose of this control is to adapt the signal to the frequency. Two bits enable the user to select High or Low Drive for memory data/addresses/control signals. Setting the EBI_DRIVE field [17:16] in the EBI Chip Select Assignement Register (EBI_CSA) located in the Chip Select Interface of the Bus Matrix, enables control of the EBI. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 27 ...
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... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 Kbytes. Figure 9-1 on page 29 Figure 8-1 on page 20 peripherals. AT91SAM9XE128/256/512 Preliminary 28 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 6254C–ATARM–22-Jan-10 ...
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... System Controller Block Diagram Figure 9-1. AT91SAM9XE128/256/512 System Controller Block Diagram periph_irq[2..24] efc2_irq pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset BOD VDDCORE VDDCORE POR NRST VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSCSEL SLOW XIN32 CLOCK OSC XOUT32 ...
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... At reset the NRST pin is an output 9.3 Brownout Detector and Power-on Reset The AT91SAM9XE128/256/512 embeds one brownout detection circuit and power-on reset cells. The power-on reset are supplied with and monitor VDDCORE and VDDBU. Signals (flash_poe and flash_wrdis) are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply ...
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... Real-time Timer with 32-bit free-running back-up counter • Integrates a 16-bit programmable prescaler running on slow clock • Alarm Register capable to generate a wake-up of the system through the Shutdown Controller 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary processor stopped waiting for an interrupt ® ® /WindowsCE ...
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... Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from AT91SAM9XE128/256/512 Preliminary 32 enabled processor Generator the ARM Processor’ ...
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... Chip Identification • Chip ID: – 0x329AA3A0 for the SAM9XE512 – 0x329A93A0 for the SAM9XE256 – 0x329973A0 for the SAM9XE128 • JTAG ID: 05B1_C03F • ARM926 TAP ID: 0x0792603F 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 33 ...
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... Peripheral Identifier The AT91SAM9XE128/256/512 embeds a wide range of peripherals. Peripheral Identifiers of the AT91SAM9XE128/256/512. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. ...
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... IDs. 10.3 Peripheral Signals Multiplexing on I/O Lines The AT91SAM9XE128/256/512 features 3 PIO controllers, PIOA, PIOB, PIOC, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following sections define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... PA27 TIOA1 ERXCK PA28 TIOA2 ECRS PA29 SCK1 ECOL (1) PA30 SCK2 RXD4 (1) PA31 SCK0 TXD4 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9XE128/256/512 Preliminary 36 Reset Power Comments State Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ...
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... RI0 PB26 RTS0 PB27 CTS0 PB28 RTS1 PB29 CTS1 PB30 PCK0 PB31 PCK1 Note: 1. Not available in the 208-lead PQFP package. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Peripheral B Comments Reset State TIOA3 I/O TIOB3 I/O TIOA4 I/O TIOA5 I/O I/O I/O TCLK1 I/O ...
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... PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9XE128/256/512 Preliminary 38 Application Usage Comments Reset State Power Supply AD0 I/O VDDANA AD1 I/O VDDANA AD2 I/O VDDANA AD3 I/O ...
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... Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary peripherals Sensors and data per chip select 39 ...
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... MCI has two slot, each supporting – One slot for one MultiMediaCard bus ( cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write AT91SAM9XE128/256/512 Preliminary TDM Buses, Magnetic Card Reader, etc.) 6254C–ATARM–22-Jan-10 ...
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... ITU-R BT. 601/656 8-bit mode external interface support • Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 41 ...
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... Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals AT91SAM9XE128/256/512 Preliminary 42 6254C–ATARM–22-Jan-10 ...
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... AMBA AHB bus interfaces • separate instruction and data TCM interfaces Table 11-1. Owner-Reference ARM Ltd. - DD10198B ARM Ltd. - DD10222B 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary ™ integer core Reference Document Table ™ family of general-purpose microproces- Denomination ...
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... Block Diagram Figure 11-1. ARM926EJ-S Internal Functional Block Diagram CP15 System Configuration Coprocessor Write Data DTCM Interface Data TCM Data Cache AT91SAM9XE128/256/512 Preliminary 44 External Coprocessors External Coprocessor Interface ARM9EJ-S Processor Core Instruction Read Data Data Instruction Address Address MMU Instruction ...
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... ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 45 ...
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... Mode changes may be made under software control, or may be brought about by external inter- rupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. AT91SAM9XE128/256/512 Preliminary 46 6254C–ATARM–22-Jan-10 ...
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... FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val- 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary shows all the registers in all modes. ARM9TDMI Modes and Registers Layout ...
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... ALU operation • control the enabling and disabling of interrupts • set the processor operation mode Figure 11-2. Status Register Format Figure 11-2 • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags AT91SAM9XE128/256/512 Preliminary ...
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... Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for exam- ple, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 49 ...
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... ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the ARM Technical Reference Manual referenced in 43. AT91SAM9XE128/256/512 Preliminary 50 into LR (current PC(r15 depending on the exception). (current depending on the exception) that causes the program to resume from the correct place on return. ...
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... MSR BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register B ...
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... Table 11-3 ence Manual referenced in Table 11-4 Table 11-4. Mnemonic MOV ADD SUB CMP TST AT91SAM9XE128/256/512 Preliminary 52 New ARM Instruction Mnemonic List Operation Branch and exchange to Java (1) Branch, Link and exchange Signed Multiply Accumulate bit Signed Multiply Accumulate Long Signed Multiply Accumulate 32 * ...
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... TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Thumb Instruction Mnemonic List (Continued) Operation Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply ...
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... Table 11-5. Register Notes: AT91SAM9XE128/256/512 Preliminary 54 CP15 Registers Name 7 Cache Operations 8 TLB operations (2) 9 cache lockdown 9 TCM region 10 TLB lockdown 11 Reserved 12 Reserved (1) 13 FCSE PID (1) 13 Context ID 14 Reserved 15 Test configuration 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field ...
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... L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 ...
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... Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- AT91SAM9XE128/256/512 Preliminary 56 shows the different attributes of each page in the physical memory. ...
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... The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 57 ...
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... Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the AT91SAM9XE128/256/512 Preliminary 58 6254C–ATARM–22-Jan-10 ...
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... When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 59 ...
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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. AT91SAM9XE128/256/512 Preliminary 60 gives an overview of the supported transfers and different kinds of transactions they Single transfer of word, half word, or byte: • ...
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... SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communica- tion Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 61 ...
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... Block Diagram Figure 12-1. Debug and Test Block Diagram TAP: Test Access Port AT91SAM9XE128/256/512 Preliminary 62 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test DTXD DRXD 6254C–ATARM–22-Jan-10 ...
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... A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary shows a complete debug environment example. The ICE/JTAG inter- ICE/JTAG Interface ...
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... Pin Name NRST TST NTRST TCK TDI TDO TMS RTCK JTAGSEL DRXD DTXD AT91SAM9XE128/256/512 Preliminary 64 shows a test environment example. Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n Connector AT91SAM9XE AT91SAM9XE-based Application Board In Test Debug and Test Pin List ...
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... A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9XE Debug Unit Chip ID value is 0x0198 03A0 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary ). DDI 0222A 65 ...
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... AT91SAM9XE128/256/512 Preliminary 66 Pin Name Pin Type A0 IN/OUT A1 IN/OUT A10 IN/OUT A11 IN/OUT A12 IN/OUT A13 IN/OUT A14 IN/OUT A15 IN/OUT A16 ...
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... Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 285 A19 284 283 A2 282 281 A20 280 279 A21 278 277 A22 276 275 A3 274 273 A4 272 271 A5 270 269 A6 268 267 A7 266 265 A8 264 263 A9 262 261 BMS ...
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... AT91SAM9XE128/256/512 Preliminary 68 D14 IN/OUT D15 IN/OUT D2 IN/OUT D3 IN/OUT D4 IN/OUT D5 IN/OUT D6 IN/OUT D7 IN/OUT D8 IN/OUT D9 IN/OUT NANDOE IN/OUT NANDWE ...
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... Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 207 PA0 206 205 PA1 204 203 PA10 202 201 PA11 200 199 PA12 198 197 PA13 196 195 PA14 194 193 PA15 192 191 PA16 190 189 PA17 188 ...
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... AT91SAM9XE128/256/512 Preliminary 70 PA27 IN/OUT PA28 IN/OUT PA29 IN/OUT PA3 IN/OUT internal internal internal internal PA4 IN/OUT PA5 IN/OUT PA6 IN/OUT PA7 ...
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... Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 127 PB16 126 125 PB17 124 123 PB18 122 121 PB19 120 119 PB2 118 117 PB20 116 115 PB21 114 113 PB22 112 111 PB23 110 109 PB24 108 ...
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... Table 12-2.AT91SAM9XE JTAG Boundary Scan Register AT91SAM9XE128/256/512 Preliminary 72 87 PB6 86 85 PB7 84 83 PB8 82 81 PB9 80 79 PC0 78 77 PC1 76 75 PC10 74 73 PC11 PC13 68 67 PC14 66 65 PC15 64 63 PC16 62 61 PC17 60 59 PC18 58 57 PC19 PC20 52 51 PC21 50 49 ...
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... Table 12-2.AT91SAM9XE JTAG Boundary Scan Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 47 PC23 46 45 PC24 44 43 PC25 42 41 PC26 40 39 PC27 38 37 PC28 36 35 PC29 PC30 30 29 PC31 28 27 PC4 26 25 PC5 24 23 PC6 22 21 PC7 20 19 PC8 18 17 PC9 16 15 RAS ...
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... VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B13 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B1_303F. AT91SAM9XE128/256/512 Preliminary 74 07 SDCKE 06 05 SDWE 04 03 SHDN ...
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... SAM-BA Boot is then executed. It waits for transactions either on the USB device the DBGU serial port. 13.2 Flow Diagram The Boot Program implements the algorithm in Figure 13-1. Boot Program Algorithm Flow Diagram Internal RC Oscillator No Crystal Table 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Start Yes Main Oscillator Bypass No Large Reduced Crystal Table No USB Enumeration ...
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... If an external 32768 Hz Oscillator is used (OSCSEL = 1) (OSCSEL = 1 and bypass Table 13-3. 3.0 4.433619 6.144 7.864320 12.0 16.0 Note: AT91SAM9XE128/256/512 Preliminary 76 13-1 defines the crystals supported by the Boot Program when using the internal RC oscillator. Reduced Crystal Table (MHz) OSCSEL = 0 3.0 6.0 Yes Yes ...
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... Figure 13-2. Clocks and DBGU Configurations No Scan Large Crystal Table (Table 15.3 &15.4) MCK = PLLB/2 UDPCK = PLLB/2 "ROMBoot>" displayed on DBGU End 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Start Yes Internal RC Oscillator? (OSCSEL = 0) Scan Reduced Table (Table 15.1 &15.2) MCK = Mosc UDPCK = PLLB/2 ...
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... In parallel, wait for character(s) received on the DBGU if MCK is configured to 48 – If not, the auto baud rate sequence is executed in parallel (see Figure 13-3. Auto Baud Rate Flow Diagram – Once the communication interface is identified, the application runs in an infinite AT91SAM9XE128/256/512 Preliminary 78 MHz (OSCSEL = 1). Device ...
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... Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Commands Available through the SAM-BA Boot Action Argument(s) write a byte Address, Value# ...
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... PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows AT91SAM9XE128/256/512 Preliminary 80 to 01) shows a transmission using this protocol. ...
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... BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Handled Standard Requests Definition Returns the current device configuration value. ...
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... Initialize the function pointer (retrieve function address from SWI vector Send your data to the sector */ /* build the command to send to EFC */ /* Call the IAP function with appropriate command */ } AT91SAM9XE128/256/512 Preliminary 82 unsigned long FlashSectorNum = 200; unsigned long flash_cmd = 0; unsigned long flash_status = 0; IAP_Function = ((unsigned long) (*)(unsigned long)) 0x100008; ...
Page 83
... Table 13-7. Peripheral DBGU DBGU 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Table 13-2 and Table 13-3 on page 76 contains a list of pins that are driven during the boot program execution. These pins Pins Driven during Boot Program Execution ...
Page 84
... AT91SAM9XE128/256/512 Preliminary 84 6254C–ATARM–22-Jan-10 ...
Page 85
... Signal Description List Signal Name Function VDDBU Backup Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL Power Supply GND Ground 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary TST VDDBU PGMEN0 VDDIO VDDIO PGMEN1 GND PGMEN2 GND PGMEN3 NCMD PGMNCMD RDY ...
Page 86
... Depending on the MODE settings, DATA is latched in different internal registers. Table 14-2. MODE[3:0] 0000 0001 0010 0011 0100 0101 Default When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. AT91SAM9XE128/256/512 Preliminary 86 Type Clocks Input Test Input Input Input Input Input PIO ...
Page 87
... NCMD signal. The handshaking is achieved once NCMD signal is high and RDY is high. 14.2.4.1 Write Handshaking For details on the write handshaking sequence, refer to 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Command Bit Coding Symbol READ WP WPL ...
Page 88
... Waits for RDY low 4 Releases MODE and DATA signals 5 Sets NCMD signal 6 Waits for RDY high 14.2.4.2 Read Handshaking For details on the read handshaking sequence, refer to Figure 14-3. AT91SAM9XE128/256/512 Preliminary 88 NCMD 2 3 RDY NOE NVALID DATA[15:0] 1 MODE[3:0] Device Action Waits for NCMD low ...
Page 89
... AT91SAM9XE128/256/512 Preliminary Device Action Waits for NCMD low Latch MODE and DATA Clears RDY signal Waits for NOE Low Sets DATA bus in output mode and outputs the flash contents. Clears NVALID signal Waits for NOE high ...
Page 90
... However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. 14.2.5.3 Flash Full Erase Command This command is used to erase the Flash memory planes. AT91SAM9XE128/256/512 Preliminary 90 Read Command Handshake Sequence MODE[3:0] Read handshaking ...
Page 91
... All the general-purpose NVM bits are also cleared by the EA command. The general-pur- pose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. Table 14-12. Set/Clear GP NVM Command Step 1 2 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Full Erase Command Handshake Sequence Write handshaking Write handshaking Handshake Sequence Write handshaking ...
Page 92
... This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 14-15. Write Command Step ... n AT91SAM9XE128/256/512 Preliminary 92 Handshake Sequence MODE[3:0] Write handshaking CMDE Read handshaking DATA Handshake Sequence MODE[3:0] Write handshaking CMDE ...
Page 93
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 14-16. Get Version Command Step 1 2 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Handshake Sequence MODE[3:0] Write handshaking ADDR1 Write handshaking DATA Write handshaking DATA ... ...
Page 94
... I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL Power Supply GND Ground Main Clock Input. This input can be tied to GND. In this XIN case, the device is clocked by the internal RC oscillator. AT91SAM9XE128/256/512 Preliminary 94 TST VDDBU VDDIO PGMEN0 VDDIO PGMEN1 GND PGMEN2 GND PGMEN3 ...
Page 95
... Shift 0x2 into the DR register ( bits long, LSB first) without going through the Run- Test-Idle state. • Shift 0xC into the IR register ( bits long, LSB first) without going through the Run-Test- Idle state. Note: Table 14-18. Reset TAP Controller and Go to Select-DR-Scan 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Type Test Input Input Input Input ...
Page 96
... The read handshake is done by polling the Debug Comms Control Register until the W bit is set. Once set, data can be read in the Debug Comms Data Register. 14.3.4 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 14-3 on page is reading and writing the Debug Comms Registers. AT91SAM9XE128/256/512 Preliminary r/w Address ...
Page 97
... Flash Erase Page and Write command (EWP) is equivalent to the Flash Write Command. How- ever, before programming the load buffer, the page is erased. Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL commands. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary DR Data (Number of Words to Read) << READ Address Memory [address] Memory [address+4] ...
Page 98
... In the same way, the Clear GPNVM command (CGPB) is used to clear GP NVM bits. All the general-purpose NVM bits are also cleared by the EA command. Table 14-24. Set and Clear General-purpose NVM Bit Command Read/Write Write Write AT91SAM9XE128/256/512 Preliminary 98 DR Data EA DR Data SLB or CLB ...
Page 99
... The Memory Write command (WRAM) is optimized for consecutive writes. An internal address buffer is automatically increased. Table 14-27. Write Command Read/Write Write Write Write Write Write Write 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary DR Data GGPB Bit Mask DR Data SSE DR Data (Number of Words to Write) << (WRAM) Address Memory [address] Memory [address+4] ...
Page 100
... Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 14-28. Get Version Command Read/Write Write Read AT91SAM9XE128/256/512 Preliminary 100 DR Data GVE Version 6254C–ATARM–22-Jan-10 ...
Page 101
... Processor reset line. It also resets the Watchdog Timer. • backup_nreset: Affects all the peripherals powered by VDDBU. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Reset Controller bod_rst_en Brownout Manager ...
Page 102
... The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts AT91SAM9XE128/256/512 Preliminary 102 Figure 15-2 shows the block diagram of the NRST Manager ...
Page 103
... RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs bod_rst_en ...
Page 104
... MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) AT91SAM9XE128/256/512 Preliminary 104 shows how the General Reset affects the reset signals. Startup Time Processor Startup = 3 cycles XXX EXTERNAL RESET LENGTH = 2 cycles Any Freq. 0x0 = General Reset ...
Page 105
... The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Resynch. Processor Startup 2 cycles = 3 cycles ...
Page 106
... The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered. When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset. AT91SAM9XE128/256/512 Preliminary 106 Resynch ...
Page 107
... Master Clock (MCK). They are released when the software reset is left, i.e.; syn- chronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Resynch. Processor Startup 2 cycles = 3 cycles ...
Page 108
... WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. AT91SAM9XE128/256/512 Preliminary 108 Any Resynch. ...
Page 109
... The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 15.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Any Freq. Processor Startup = 3 cycles Any XXX proc_nreset signal ...
Page 110
... Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt. Figure 15-10. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM9XE128/256/512 Preliminary 110 read RSTC_SR 2 cycle resynchronization 6254C–ATARM–22-Jan-10 Figure ...
Page 111
... Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write Reset ...
Page 112
... PERRST: Peripheral Reset effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9XE128/256/512 Preliminary 112 KEY – ...
Page 113
... Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress software command is being performed by the reset controller. The reset controller is ready for a software command software reset command is being performed by the reset controller. The reset controller is busy. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary – ...
Page 114
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9XE128/256/512 Preliminary 114 29 28 ...
Page 115
... Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary set 0 RTT_SR RTTINC ...
Page 116
... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM9XE128/256/512 Preliminary 116 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 117
... Real-time Timer (RTT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Name RTT_MR RTT_AR RTT_VR RTT_SR Access Reset Read-write 0x0000_8000 Read-write 0xFFFF_FFFF Read-only 0x0000_0000 ...
Page 118
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM9XE128/256/512 Preliminary 118 – ...
Page 119
... Defines the alarm value (ALMV+1) compared with the Real-time Timer. 16.4.3 Real-time Timer Value Register Register Name: RTT_VR Address: 0xFFFFFD28 Access Type: Read-only • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary ALMV ALMV ALMV ALMV ...
Page 120
... The Real-time Alarm occured since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM9XE128/256/512 Preliminary 120 – ...
Page 121
... Block Diagram Figure 17-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR set 0 PIT_SR PITS reset 0 ...
Page 122
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. AT91SAM9XE128/256/512 Preliminary 122 Figure 17-2 illustrates 6254C– ...
Page 123
... Figure 17-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 123 ...
Page 124
... Periodic Interval Timer (PIT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM9XE128/256/512 Preliminary 124 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset ...
Page 125
... The Periodic Interval Timer is disabled when the PIV value is reached The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary – – ...
Page 126
... PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary – – – ...
Page 127
... Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurences of periodic intervals since the last read of PIT_PIVR. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary PICNT 21 ...
Page 128
... Access Type: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurences of periodic intervals since the last read of PIT_PIVR. AT91SAM9XE128/256/512 Preliminary 128 PICNT CPIV CPIV ...
Page 129
... Block Diagram Figure 18-1. Watchdog Timer Block Diagram write WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD ...
Page 130
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM9XE128/256/512 Preliminary 130 6254C–ATARM–22-Jan-10 ...
Page 131
... Figure 18-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9XE128/256/512 Preliminary 131 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6254C–ATARM–22-Jan-10 ...
Page 132
... Watchdog Timer (WDT) User Interface Table 18-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM9XE128/256/512 Preliminary 132 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6254C–ATARM–22-Jan-10 ...
Page 133
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9XE128/256/512 Preliminary 133 KEY – – – – – ...
Page 134
... The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. AT91SAM9XE128/256/512 Preliminary 134 ...
Page 135
... WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9XE128/256/512 Preliminary 135 6254C–ATARM–22-Jan-10 ...
Page 136
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM9XE128/256/512 Preliminary 136 – ...
Page 137
... Shutdown Controller. 19.5 Functional Description The Shutdown Controller manages the main power supply so supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary read SHDW_SR reset WAKEUP0 SHDW_SR set ...
Page 138
... SHDW_SR. When using the RTT alarm to wake up the system, the user must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails. AT91SAM9XE128/256/512 Preliminary 138 6254C–ATARM–22-Jan-10 ...
Page 139
... Shutdown Controller (SHDWN) User Interface Table 19-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Name SHDW_CR SHDW_MR SHDW_SR Access Reset Write-only - Read-write 0x0000_0003 Read-only 0x0000_0000 139 ...
Page 140
... SHDW: Shutdown Command effect KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9XE128/256/512 Preliminary 140 KEY – – – – ...
Page 141
... Because of the internal synchronization of WKUP0, the SHDN pin is released (CPTWK Slow Clock cycles after the event on WKUP. • RTTWKEN: Real-time Timer Wake-up Enable 0 = The RTT Alarm signal has no effect on the Shutdown Controller The RTT Alarm signal forces the de-assertion of the SHDN pin. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary – – ...
Page 142
... At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. • RTTWK: Real-time Timer Wake- wake-up alarm from the RTT occurred since the last read of SHDW_SR least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. AT91SAM9XE128/256/512 Preliminary 142 – ...
Page 143
... The embedded Flash size, the page size, the lock regions organization and GPNVM bits defini- tion are described in the product definition section. The Enhanced Embedded Flash Controller (EEFC) returns a descriptor of the Flash controlled after a get descriptor command issued by the application (see 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary “Getting Embedded Flash Descriptor” on page 149). 143 ...
Page 144
... Figure 20-1. Embedded Flash Organization Start Address + Flash size -1 AT91SAM9XE128/256/512 Preliminary 144 Memory Plane Page 0 Start Address Page (m-1) Page (n*m-1) Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock Bit (n-1) 6254C–ATARM–22-Jan-10 ...
Page 145
... Data To ARM XXX Bytes 0-3 Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Immediate consecutive code read accesses are not mandatory to benefit from this optimization. @Byte 16 @Byte 8 @Byte 12 Bytes 16-31 Bytes 0-15 ...
Page 146
... XXX Buffer 1 (128bits) Data To ARM XXX Note: When FWS is included between 4 and 10, in case of sequential reads, the first access takes (FWS+1) cycles, each first access of the 128-bit read (FWS-2) cycles, and the others only 1 cycle. AT91SAM9XE128/256/512 Preliminary 146 @20 @ @12 @16 Bytes 16-31 ...
Page 147
... Master Clock ARM Request (32-bit) @Byte 0 Flash Access XXX Bytes 0-15 Buffer (128bits) XXX Data To ARM XXX Bytes 0-3 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary No consecutive data read accesses are mandatory to benefit from this optimization Bytes 0-15 4-7 8-11 12-15 Figure 20-5 ...
Page 148
... When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane, but the FLOCKE flag is set in the EEFC_FSR register. This flag is automatically cleared by a read access to the EEFC_FSR register. AT91SAM9XE128/256/512 Preliminary 148 Set of Commands ...
Page 149
... EEFC_FCR register. The first word of the descriptor can be read by the software application in the EEFC_FRR register as soon as the FRDY flag in the EEFC_FSR register rises. The next reads of the EEFC_FRR register provide the following word of the descriptor. If extra read oper- 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Read Status: MC_FSR No Check if FRDY flag Set ...
Page 150
... When programming is completed, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the interrupt line of the System Controller is activated. Two errors can be detected in the EEFC_FSR register after a programming sequence: AT91SAM9XE128/256/512 Preliminary 150 Word Index 0 ...
Page 151
... Lock Bit Protection Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages. The lock sequence is: 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Figure 20-7). 32-bit wide FF FF ...
Page 152
... Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the SGPB command and the number of the GPNVM bit to be set. AT91SAM9XE128/256/512 Preliminary 152 Access to the Flash in read is permitted when a set, clear or get lock bit command is performed. ...
Page 153
... Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Access to the Flash in read is permitted when a set, clear or get GPNVM bit command is performed. 153 ...
Page 154
... Offset Register EEFC 0x00 Flash Mode Register EEFC 0x04 Flash Command Register EEFC 0x08 Flash Status Register EEFC 0x0C Flash Result Register 0x10 Reserved AT91SAM9XE128/256/512 Preliminary 154 Name Access EEFC _FMR Read-write EEFC _FCR Write-only EEFC _FSR Read-only EEFC _FRR Read-only – ...
Page 155
... Flash Ready does not generate an interrupt. 1: Flash Ready (to accept a new command) generates an interrupt. • FWS: Flash Wait State This field defines the number of wait states for read and write operations: Number of cycles for Read/Write operations = FWS+1 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary – – ...
Page 156
... Field is meaningless. • FKEY: Flash Writing Protection Key This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is writ- ten with a different value, the write is not performed and no action is started. AT91SAM9XE128/256/512 Preliminary 156 29 28 ...
Page 157
... No programming/erase of at least one locked region has happened since the last read of EEFC_FSR. 1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR. This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary – ...
Page 158
... Access Type: Read-only Offset: 0x6C • FVALUE: Flash Result Value The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting value is accessible at the next register read. AT91SAM9XE128/256/512 Preliminary 158 FVALUE FVALUE FVALUE 5 ...
Page 159
... The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field allows to choose the default master type (no default, last access master, fixed default master) whereas the 4-bit 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary ® Advance Peripheral Bus and provides a 159 ...
Page 160
... Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer. 4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. AT91SAM9XE128/256/512 Preliminary 160 Section 21.4.1.2 “Slot Cycle 161). 6254C–ATARM–22-Jan-10 ...
Page 161
... This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master’s requests are active at the same time, the master with the highest priority number is serviced first. If two or 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 161 ...
Page 162
... For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS). AT91SAM9XE128/256/512 Preliminary 162 6254C–ATARM–22-Jan-10 ...
Page 163
... Priority Register A for Slave 3 0x009C Reserved 0x00A0 Priority Register A for Slave 4 0x00A8 - 0x00FC Reserved 0x0100 Master Remap Control Register 0x0104 - 0x010C Reserved 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Name MATRIX_MCFG0 MATRIX_MCFG1 MATRIX_MCFG2 MATRIX_MCFG3 MATRIX_MCFG4 MATRIX_MCFG5 – MATRIX_SCFG0 MATRIX_SCFG1 MATRIX_SCFG2 MATRIX_SCFG3 MATRIX_SCFG4 – ...
Page 164
... The undefined length burst is split into 4-beat burst allowing rearbitration at each 4-beat burst end. 3: Eight Beat Burst The undefined length burst is split into 8-beat burst allowing rearbitration at each 8-beat burst end. 4: Sixteen Beat Burst The undefined length burst is split into 16-beat burst allowing rearbitration at each 16-beat burst end. AT91SAM9XE128/256/512 Preliminary 164 – ...
Page 165
... This is the number of the Default Master for this slave. Only used if DEFMASTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMASTR_TYPE to 0. • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration 2: Reserved 3: Reserved 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary – – – 21 ...
Page 166
... RCBx: Remap Command Bit for AHB Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master AT91SAM9XE128/256/512 Preliminary 166 – – – M5PR – M3PR – ...
Page 167
... Chip Configuration User Interface Table 21-2. Chip Configuration User Interface Offset Register 0x0110 - 0x0118 Reserved 0x011C EBI Chip Select Assignment Register 0x0130 - 0x01FC Reserved 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Name – EBI_CSA – Access Reset Value – – Read-write 0x00010000 – ...
Page 168
... Value Drive Configuration 00 Optimized for 1.8V powered memories with Low Drive 01 Optimized for 3.3V powered memories with Low Drive 10 Optimized for 1.8V powered memories with High Drive 11 Optimized for 3.3V powered memories with High Drive AT91SAM9XE128/256/512 Preliminary 168 – – – – ...
Page 169
... AT91SAM9XE128/256/512 External Bus Interface 22.1 Description The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM Static Memory, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM ...
Page 170
... Block Diagram 22.2.1 External Bus Interface Figure 22-1 Figure 22-1. Organization of the External Bus Interface Bus Matrix AHB Address Decoders AT91SAM9XE128/256/512 Preliminary 170 shows the organization of the External Bus Interface. External Bus Interface SDRAM Controller MUX Static Logic Memory Controller ...
Page 171
... EBI_RAS - EBI_CAS Row and Column Signal EBI_NWR0 - EBI_NWR3 Write Signals EBI_NBS0 - EBI_NBS3 Byte Mask Signals EBI_SDA10 SDRAM Address 10 Line 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller Type Active Level I/O ...
Page 172
... EBI_A0/NBS0 EBI_A1/NBS2/NWR2 EBI_A[11:2] EBI_SDA10 EBI_A12 EBI_A[14:13] EBI_A[22:15] EBI_A[25:23] EBI_D[31:0] AT91SAM9XE128/256/512 Preliminary 172 details the connections between the two Memory Controllers and the EBI Pins and Memory Controllers I/O Lines Connections EBIx Pins SDRAMC I/O Lines NBS1 Not Supported Not Supported SDRAMC_A[9:0] ...
Page 173
... NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. 4. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. 5. BEx: Byte x Enable ( 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary details the connections to be applied between the EBI pins and the Pins of the Interfaced Device 2 x 8-bit ...
Page 174
... A18 - A20 A21 A22 A23 - A24 A25 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NCS6 NCS7 NANDOE NANDWE NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CFCE1 AT91SAM9XE128/256/512 Preliminary 174 Pins of the Interfaced Device CompactFlash SDRAM (EBI only) SDRAMC D15 D16 - D31 – DQM0 A0 DQM2 A1 A[0:8] A[2:10] A9 – ...
Page 175
... Pxx Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2. Any PIO line. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Pins of the Interfaced Device CompactFlash SDRAM (EBI only) SDRAMC – ...
Page 176
... It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: • the Static Memory Controller (SMC) • the SDRAM Controller (SDRAMC) AT91SAM9XE128/256/512 Preliminary 176 shows an example of connections between the EBI and external devices. EBI ...
Page 177
... FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are sup- ported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 177 ...
Page 178
... Register (DBW field in the corresponding Chip Select Register) of the NCS4 and/or NCS5 address space must be set as shown in NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select. AT91SAM9XE128/256/512 Preliminary 178 178. Offset 0x00E0 0000 ...
Page 179
... CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. 22-4 on page 180 Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary CFCE1 DBW Comment NBS0 ...
Page 180
... EBI_CSA Register in the Chip Configuration User Interface is set. These pins must not be used to drive any other memory devices. The EBI pins in responding CompactFlash interface is enabled (EBI_CS4A = 1 and/or EBI_CS5A = 1). Table 22-8. Dedicated CompactFlash Interface Multiplexing Pins CS4A = 1 NCS4/CFCS0 CFCS0 NCS5/CFCS1 AT91SAM9XE128/256/512 Preliminary 180 External Bus Interface SMC A23 A22 NRD_NOE NWR0_NWE CFWE NWR0_NWE 1 ...
Page 181
... The CompactFlash _WAIT sig- nal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller Section. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Access to CompactFlash Device CompactFlash Signals CFOE ...
Page 182
... NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. See Figure Signal Multiplexing on EBI Pins” on page 183 forms, refer to the Static Memory Controller section. AT91SAM9XE128/256/512 Preliminary 182 EBI D[15:0] ...
Page 183
... NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) sig- nals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary SMC NCSx NRD_NOE ...
Page 184
... Figure 22-7. NAND Flash Application Example Note: AT91SAM9XE128/256/512 Preliminary 184 D[7:0] A[22:21] NCSx/NANDCS Not Connected EBI NANDOE NANDWE PIO PIO The External Bus Interface is also able to support 16-bit devices. AD[7:0] ALE CLE NAND Flash NOE NWE CE R/B 6254C–ATARM–22-Jan-10 ...
Page 185
... Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width programmed to 16 bits. The SDRAM initialization sequence is described in the “SDRAM device initialization” part of the SDRAM controller. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary D[0..15] A[0..14] (Not used A12) A2 ...
Page 186
... The Data Bus Width programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the “SDRAM device initialization” part of the SDRAM controller. AT91SAM9XE128/256/512 Preliminary 186 ...
Page 187
... Configure a PIO line as an input to manage the Ready/Busy signal. • Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND Flash timings, the data bus width and the system bus frequency. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary D[0..7] CLE ALE ...
Page 188
... NAND FLASH Hardware Configuration 22.7.4.1 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode register of the Static Memory Controller. AT91SAM9XE128/256/512 Preliminary 188 D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) ...
Page 189
... The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary D[0..15] A[1..22 ...
Page 190
... A[0..10] A10 A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT AT91SAM9XE128/256/512 Preliminary 190 MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 B1 B6 1B4 1A4 CF_D11 ...
Page 191
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode according to Compact Flash timings and system bus frequency. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 191 ...
Page 192
... A[0..10] A10 3V3 A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT AT91SAM9XE128/256/512 Preliminary 192 MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 B1 B6 1B4 1A4 CF_D11 C2 ...
Page 193
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode according to Compact Flash timings and system bus frequency. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary 193 ...
Page 194
... AT91SAM9XE128/256/512 Preliminary 194 6254C–ATARM–22-Jan-10 ...
Page 195
... NBS1 A1 NWR2 NBS2 NWR3 NBS3 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Related Function Byte-write or byte-select access, see 8-bit or 16-/32-bit data bus, see “Data Bus Width” on page 197 Byte-write or byte-select access see “Byte Write or Byte Select Access” on page 197 8-/16-bit or 32-bit data bus, see “ ...
Page 196
... The programmer must first program the PIO controller to assign the Static Memory Con- troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other purposes by the PIO Controller. AT91SAM9XE128/256/512 Preliminary 196 128K x 8 ...
Page 197
... Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select. 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary NCS2 NCS1 NCS0 shows how to connect a 512K x 8-bit memory on NCS2 ...
Page 198
... Figure 23-3. Figure 23-4. Figure 23-5. Memory Connection for a 32-bit Data Bus AT91SAM9XE128/256/512 Preliminary 198 Memory Connection for an 8-bit Data Bus D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] Memory Connection for a 16-bit Data Bus D[15:0] A[19:2] A1 NBS0 SMC NBS1 NWE NRD NCS[2] ...
Page 199
... Byte Select Access is used to connect two 16-bit devices. Figure 23-7 mode, on NCS3 (BAT = Byte Select Access). 6254C–ATARM–22-Jan-10 AT91SAM9XE128/256/512 Preliminary Figure 23-6. shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access 199 ...
Page 200
... For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused. AT91SAM9XE128/256/512 Preliminary 200 Connection 8-bit Devices on a 16-bit Bus: Byte Write Option ...