LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 14

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 3.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
LPC1769_68_67_66_65_64_4
Product data sheet
Symbol
RTCX2
V
V
V
V
V
VREFP
VREFN
VBAT
n.c.
SS
SSA
DD(3V3)
DD(REG)(3V3)
DDA
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled and the pin is not 5 V tolerant.
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
Open-drain 5 V tolerant digital I/O pad, compatible with I
output functionality. When power is switched off, this pin connected to the I
Open-drain configuration applies to all functions on this pin.
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
Pad provides special analog functionality.
When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
Pin description
Pin
18
31, 41,
55, 72,
97, 83
11
28, 54,
71, 96
42, 84
10
12
15
19
13
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
…continued
Type
O
I
I
I
I
I
I
I
I
-
Description
Output from the RTC oscillator circuit.
ground: 0 V reference.
analog ground: 0 V reference. This should nominally be the same voltage as V
but should be isolated to minimize noise and error.
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip
voltage regulator only.
analog 3.3 V pad supply voltage: This should be nominally the same voltage as
V
power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are
not used.
ADC positive reference voltage: This should be nominally the same voltage as
V
as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and
DAC are not used.
ADC negative reference voltage: This should be nominally the same voltage as
V
a reference for ADC and DAC.
RTC pin power supply: 3.3 V on this pin supplies the power to the RTC
peripheral.
not connected.
DD(3V3)
DDA
SS
but should be isolated to minimize noise and error. Level on this pin is used as
but should be isolated to minimize noise and error. Level on this pin is used
Rev. 04 — 1 February 2010
but should be isolated to minimize noise and error. This voltage is used to
2
C-bus 400 kHz specification. This pad requires an external pull-up to provide
LPC1769/68/67/66/65/64
2
C-bus is floating and does not disturb the I
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2010. All rights reserved.
2
C lines.
14 of 66
SS
,