Z8F0213PJ005SC Zilog, Z8F0213PJ005SC Datasheet - Page 177

• Manufacturer Part Number: Z8F0213PJ005SC
• Description: IC ENCORE MCU FLASH 2K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0213PJ005SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3461

Table 102. Oscillator Control Register (OSCCTL)
Oscillator Control Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
Caution:
Oscillator Control Register
INTEN
R/W
7
1
Watchdog Timer Failure
In the event of a Watchdog Timer oscillator failure, a similar non-maskable interrupt-like
event is issued. This event does not trigger an attendant clock switch-over, but alerts the
CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a
primary oscillator failure. The failure detection circuitry does not function if the Watchdog
Timer is used as the primary oscillator or if the Watchdog Timer oscillator has been dis-
abled. For either of these cases, it is necessary to disable the detection circuitry by deas-
serting the
The Watchdog Timer oscillator failure detection circuit counts system clocks while
searching for a Watchdog Timer clock. The logic counts 8004 system clock cycles before
determining that a failure has occurred. The system clock rate determines the speed at
which the Watchdog Timer failure can be detected. A very slow system clock results in
very slow detection times.
The following section provides the bit definitions for the Oscillator Control register.
The Oscillator Control register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry and selects the primary oscillator,
which becomes the system clock.
The Oscillator Control register must be unlocked before writing. Writing the two step
sequence
is locked at successful completion of a register write to the OSCCTL.
It is possible to disable the clock failure detection circuitry as well as all functioning
clock sources. In this case, the Z8 Encore! XP F0823 Series device ceases functioning
and can only be recovered by Power-On Reset.
Reserved
E7H
R/W
WDFEN
6
0
followed by
bit of the OSCCTL register.
WDTEN
R/W
5
1
18H
to the Oscillator Control Register unlocks it. The register
POFEN
R/W
4
0
F86H
WDFEN
R/W
3
0
Z8 Encore! XP
R/W
2
0
Product Specification
SCKSEL
R/W
1
0
®
Oscillator Control
F0823 Series
R/W
0
0
167