MC908JL16CFJER Freescale Semiconductor, MC908JL16CFJER Datasheet - Page 45

• Manufacturer Part Number: MC908JL16CFJER
• Description: IC MCU 8BIT 16K FLASH 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CFJER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 26
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: MC908JL16CFJERTR

Chapter 4
System Integration Module (SIM)
4.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM
is shown in
controller that coordinates CPU and exception timing. The SIM is responsible for:
Freescale Semiconductor
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Signal Name
OSCOUT
PORRST
Bus clock generation and control for CPU and peripherals
–
–
Master reset control, including power-on reset (POR) and COP timeout
Interrupt control:
–
–
–
CPU enable/disable timing
Modular architecture expandable to 128 interrupt sources
IRST
ICLK
R/W
IAB
IDB
Stop/wait/reset/break entry and recovery
Internal clock control
Acknowledge timing
Arbitration control timing
Vector address generation
Figure
4-1.
Internal oscillator clock
The XTAL or RC frequency divided by two. This signal is again divided by two in the SIM to
generate the internal bus clocks. (Bus clock = OSCOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Figure 4-2
Table 4-1. Signal Name Conventions
is a summary of the SIM I/O registers. The SIM is a system state
MC68HC908JL16 Data Sheet, Rev. 1.1
Description
45