C8051F819-GM Silicon Laboratories Inc, C8051F819-GM Datasheet - Page 144

IC MCU 8BIT 8KB FLASH 20QFN

C8051F819-GM

Manufacturer Part Number
C8051F819-GM
Description
IC MCU 8BIT 8KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F81xr
Datasheet

Specifications of C8051F819-GM

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051F8x
Core
8051
Data Bus Width
16 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F800DK
Minimum Operating Temperature
- 55 C
Package
20QFN EP
Device Core
8051
Family Name
C8051F8xx
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
336-1799-5
C8051F80x-83x
144
Figure 23.4. Priority Crossbar Decoder Potential Pin Assignments
Pins P0.0-P1.7
The crossbar peripherals are assigned in priority order from top to bottom,
according to this diagram.
a peripheral.
these signals are enabled, the Crossbar should be manually configured to
skip the corresponding port pins.
Notes:
1. P1.4-P1.7 are not available on 16-pin packages.
2. NSS is only pinned out when the SPI is in 4-wire mode.
Pin Number
These boxes represent Port pins which can potentially be assigned to
Special Function Signals are not assigned by the crossbar. When
Pins can be “skipped” by setting the corresponding bit in PnSKIP to ‘1’.
SYSCLK
Function
Pin Skip
Settings
Special
Signals
CP0A
CEX0
CEX1
CEX2
MISO
MOSI
NSS
SCK
SDA
RX0
SCL
CP0
Port
TX0
ECI
T0
T1
2
0
0
1
are capable of being assigned to crossbar peripherals.
1
0
2
0
P0SKIP
3
0
P0
4
0
5
0
Rev. 1.0
6
0
7
0
0
0
1
0
2
0
P1SKIP
3
0
P1
4
0
1
5
0
1
6
0
1
7
0
1
0

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