C8051F819-GM Silicon Laboratories Inc, C8051F819-GM Datasheet - Page 50

IC MCU 8BIT 8KB FLASH 20QFN

C8051F819-GM

Manufacturer Part Number
C8051F819-GM
Description
IC MCU 8BIT 8KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F81xr
Datasheet

Specifications of C8051F819-GM

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051F8x
Core
8051
Data Bus Width
16 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F800DK
Minimum Operating Temperature
- 55 C
Package
20QFN EP
Device Core
8051
Family Name
C8051F8xx
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
336-1799-5
C8051F80x-83x
SFR Definition 8.1. ADC0CF: ADC0 Configuration
SFR Address = 0xBC
50
Name
Reset
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
Bit
Type
2
1
0
Bit
AMP0GN0 ADC Gain Control Bit.
AD0LJST
AD08BE
Name
7
1
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
0: Gain = 0.5
1: Gain = 1
AD0SC
6
1
=
AD0SC[4:0]
SYSCLK
---------------------- - 1
CLK
R/W
5
1
SAR
Rev. 1.0
4
1
Function
3
1
AD0LJST
R/W
2
0
AD08BE
R/W
1
0
AMP0GN0
R/W
0
1

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