C8051F813-GM Silicon Laboratories Inc, C8051F813-GM Datasheet - Page 157

• Manufacturer Part Number: C8051F813-GM
• Description: IC MCU 8BIT 8KB FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F81xr

Specifications of C8051F813-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Processor Series: C8051F8x
• Core: 8051
• Data Bus Width: 16 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F800DK
• Minimum Operating Temperature: - 55 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1786-5

SFR Definition 23.14. P1SKIP: Port 1 Skip
SFR Address = 0xD5
SFR Definition 23.15. P2: Port 2
SFR Address = 0xA0; Bit-Addressable
Name
Reset
Name
Reset
Bit
7:0
Bit
7:1
Type
Type
0
Bit
Bit
Unused
P1SKIP[7:0]
Name
P2[0]
Name
0*
R
7
7
0
Unused.
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
Note: P1.4–P1.7 are not available on 16-pin packages, with the reset value of 1111b for
0*
R
6
6
0
Description
P1SKIP[7:4].
0*
R
5
5
0
Rev. 1.0
Don’t Care
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
0*
R
4
4
0
P1SKIP[7:0]
R/W
Function
Write
R
3
0
3
0
C8051F80x-83x
R
2
0
2
0
0000000b
0: P2.0 Port pin is logic
LOW.
1: P2.0 Port pin is logic
HIGH.
R
1
0
1
0
Read
P2[0]
R/W
0
0
0
1
157