C8051F813-GM Silicon Laboratories Inc, C8051F813-GM Datasheet - Page 234

• Manufacturer Part Number: C8051F813-GM
• Description: IC MCU 8BIT 8KB FLASH 20QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F81xr

Specifications of C8051F813-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-QFN
• Processor Series: C8051F8x
• Core: 8051
• Data Bus Width: 16 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F800DK
• Minimum Operating Temperature: - 55 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1786-5

C8051F80x-83x
29.3.5.2. 9-bit through 15-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in N-bit PWM mode (N=9 through 15) should be varied by writing
to an “Auto-Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register loca-
tions. The data written to define the duty cycle should be right-justified in the registers. The auto-reload
registers are accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/com-
pare registers are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 29.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM. This synchronous update feature
allows software to asynchronously write a new PWM high time, which will then take effect on the following
PWM period.
The 9, 10, 11, 12, 13, 14, or 15-bit PWM mode is selected by setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other
than 8-bits). If the MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator
match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge),
which will occur every 512 (9-bit), 1024 (10-bit), 2048 (11-bit), 4096 (12-bit), 8192 (13-bit), 16384 (14-bit),
or 32768 (15-bit) PCA clock cycles. The duty cycle for n-Bit PWM Mode (n=9 through 15) is given in
Equation 29.2, where N is the number of bits in the PWM cycle. A 0% duty cycle may be generated by
clearing the ECOMn bit to 0.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
234
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
1
Figure 29.9. PCA 9-bit through 15-Bit PWM Mode Diagram
Equation 29.3. N-Bit PWM Duty Cycle (N=9 through 15)
P
W
M
1
6
n
0
E
C
O
M
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
C
A
P
N
n
M
A
T
n
O
G
T
n
W
M
P
n
C
C
E
F
n
x
Duty Cycle
PCA Timebase
ARSEL = 1
ARSEL = 0
R/W when
R/W when
Enable
N-bit Comparator
(Capture/Compare)
=
PCA0CPH:Ln
PCA0CPH:Ln
(Auto-Reload)
(right-justified)
(right-justified)
Rev. 1.0
PCA0H:L

------------------------------------------- -
2
N
–
PCA0CPn
2
N
Overflow of N
Match
th
A
R
S
E
L
Bit

O
S
R
PCA0PWM
E
C
V
x
O
C
V
F
SET
CLR
E
A
R
Q
Q
1
6
x
C
S
E
L
L
2
C
S
E
L
L
1
CEXn
C
S
E
L
L
0
Set “N” bits:
001 = 9 bits
010 = 10 bits
011 = 11 bits
Crossbar
100 = 12 bits
101 = 13 bits
110 = 14 bits
111 = 15 bits
Port I/O