MCHC908JW32FC Freescale Semiconductor, MCHC908JW32FC Datasheet - Page 38

• Manufacturer Part Number: MCHC908JW32FC
• Description: IC MCU 32K FLASH 8MHZ 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FC

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-QFN
• Controller Family/series: HC08
• No. Of I/o's: 29
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI, USB
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Memory
This program sequence is repeated throughout the memory until all data is programmed.
2.5.6 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target
application, provision is made to protect pages of memory from unintentional erase or program operations
due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the
protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory
($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program
operations.
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The time between each FLASH address change (step 6 to step 6), or the
time between the last FLASH addressed programmed to clearing the PGM
bit (step 6 to step 9), must not exceed the maximum programming time,
t
Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps.
The 48 bytes of user interrupt vectors ($FFD0–$FFFF) are always
protected, regardless of the value in the FLASH block protect register. A
mass erase is required to erase these locations.
prog
max.
MC68HC908JW32 Data Sheet, Rev. 6
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Freescale Semiconductor