MCHC908JW32FC Freescale Semiconductor, MCHC908JW32FC Datasheet - Page 68

• Manufacturer Part Number: MCHC908JW32FC
• Description: IC MCU 32K FLASH 8MHZ 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FC

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-QFN
• Controller Family/series: HC08
• No. Of I/o's: 29
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI, USB
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Clock Generator Module (CGM)
BCS — Base Clock Select Bit
PRE1 and PRE0 — Prescaler Program Bits
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
68
This read/write bit selects either the oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as
the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the
selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to
three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the
other. During the transition, CGMOUT is held in stasis. (See
clears the BCS bit.
These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See
5.3.3 PLL Circuits
PLLON bit is set. Reset clears these bits.
These prescaler bits affects the relationship between the VCO clock and the final system bus clock.
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L (See
Register.) controls the hardware center-of-range frequency, f
the PLLON bit is set. Reset clears these bits.
1 = CGMVCLK divided by three drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
5.3.8 Base Clock Selector
5.3.3 PLL
NOTE: Do not program E to a value of 3.
and
PRE1 and PRE0
VPR1 and VPR0
Circuits,
5.3.6 Programming the
00
01
10
11
00
01
10
Table 5-2. PRE1 and PRE0 Programming
Table 5-3. VPR1 and VPR0 Programming
5.3.6 Programming the
MC68HC908JW32 Data Sheet, Rev. 6
Circuit.)
NOTE
PLL.) PRE1 and PRE0 cannot be written when the
P
E
0
1
2
3
0
1
2
PLL, and
5.3.8 Base Clock Selector
VRS
Prescaler Multiplier
VCO Power-of-Two
. VPR1:VPR0 cannot be written when
Range Multiplier
5.5.4 PLL VCO Range Select
1
2
4
8
1
2
4
Freescale Semiconductor
Circuit.) Reset