MCHC908JW32FC Freescale Semiconductor, MCHC908JW32FC Datasheet - Page 42

• Manufacturer Part Number: MCHC908JW32FC
• Description: IC MCU 32K FLASH 8MHZ 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908JW32FC

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-QFN
• Controller Family/series: HC08
• No. Of I/o's: 29
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SPI, USB
• Rohs Compliant: Yes
• Processor Series: HC08JW
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USB
• Number Of Programmable I/os: 29
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Configuration Registers (CONFIG)
3.3 Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select
LVISTOP — Low Voltage Inhibit Enable in STOP mode bit
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
SSREC — Short Stop Recovery
42
COPRS selects the COP time-out period. Reset clears COPRS. (See
Properly
When the LVIPWRD bit is clear or the LVIREGD is clear, setting the LVISTOP bit enables the LVI to
operate during STOP mode. Reset clears LVISTOP.
LVIRSTD disables the reset signal from the LVI module.
LVIPWRD disables the LVI module completely. When it is set, LVI trip for V
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096
CGMXCLK cycle delay.
1 = COP time out period = 8176 CGMRCLK cycles
0 = COP time out period = 262,128 CGMRCLK cycles
1 = Low voltage inhibit enabled during stop mode
0 = Low voltage inhibit disable during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power and LVI trip for V
0 = LVI module power and LVI trip for V
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
(COP).)
Address:
When the LVISTOP is enabled, the system stabilization time for power on
reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay
longer than the enable time for the LVI. There is no period where the MCU
is not protected from a low power condition. However, when using the short
stop recovery configuration option, the 32 CGMXCLK delay is less than the
LVI’s turn-on time and there exists a period in start-up where the LVI is not
protecting the MCU.
Reset:
Read:
Write:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
COPRS
$001F
Bit 7
0
Figure 3-2. Configuration Register 1 (CONFIG1)
= Unimplemented
LVISTOP
6
0
MC68HC908JW32 Data Sheet, Rev. 6
LVIRSTD
5
0
DD
DD
LVIPWRD
NOTE
NOTE
disabled
is enabled
4
0
3
0
SSREC
2
0
Chapter 16 Computer Operating
STOP
1
0
DD
is disabled.
Freescale Semiconductor
COPD
Bit 0
0