R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 128

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Table 12.3
ILVL2 to ILVL0 Bits
000b
001b
010b
011b
100b
101b
110b
111b
12.1.6.1
12.1.6.2
12.1.6.3
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupt and the I
Synchronous Serial I/O with Chip Select Interrupts, and I
Multiple Interrupt Request Sources).
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
Feb 29, 2008
Settings of Interrupt Priority
Levels
I Flag
IR Bit
Bits ILVL2 to ILVL0 and IPL
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt Priority Level
2
C bus Interface Interrupt are different. Refer to 12.5 Timer RD Interrupt, Clock
Page 109 of 485
Priority Order
High
Low
−
Table 12.4
000b
001b
010b
011b
100b
101b
110b
111b
IPL
2
C bus Interface Interrupt (Interrupts with
IPL
Interrupt Priority Levels Enabled by
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts are disabled
Enabled Interrupt Priority Levels
12. Interrupts