R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 222

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.52
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4
NOTES:
1.
2.
3. This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (TRD0 and TRD1 operate
This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
synchronously).
Feb 29, 2008
b3 b2
Registers TRDCR0 to TRDCR1 in Output Compare Function
b1 b0
Bit Symbol
TRDCR0
TRDCR1
Symbol
CKEG0
CKEG1
CCLR0
CCLR1
CCLR2
TCK0
TCK1
TCK2
Page 203 of 485
Count source select bits
External clock edge select
bits
TRDi counter clear select
bits
(2)
Address
Bit Name
0140h
0150h
b2 b1 b0
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRDCLK input
1 1 0 : fOCO40M
1 1 1 : Do not set.
b4 b3
0 0 : Count at the rising edge
0 1 : Count at the falling edge
1 0 : Count at both edges
1 1 : Do not set.
b7 b6 b5
0 0 0 : Disable clear (free-running operation)
0 0 1 : Clear by compare match w ith the
0 1 0 : Clear by compare match w ith the
0 1 1 : Synchronous clear (clear
1 0 0 : Do not set.
1 0 1 : Clear by compare match w ith the
1 1 0 : Clear by compare match w ith the
1 1 1 : Do not set.
TRDGRAi register
TRDGRBi register
simultaneously w ith other channel
counter)
TRDGRCi register
TRDGRDi register
(3)
After Reset
Function
(1)
00h
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW