R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 234

• Manufacturer Part Number: R5F21256SNFP#U0
• Description: IC R8C MCU FLASH 32K 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21256SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.63
Timer RD Start Register
Timer RD Mode Register
b7 b6 b5 b4 b3 b2
NOTES:
b7 b6 b5 b4
1.
2.
3.
4.
5.
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1
TRDSTR Register of Notes on Tim er RD .
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
Feb 29, 2008
b3 b2
Registers TRDSTR and TRDMR in PWM Mode
b1 b0
b1 b0
Bit Symbol
Bit Symbol
TSTART0
TSTART1
TRDSTR
(b7-b4)
(b3-b1)
Symbol
Symbol
TRDMR
CSEL0
CSEL1
SYNC
BFC0
BFD0
BFC1
BFD1
(1)
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TRD0 count start flag
TRD1 count start flag
TRD0 count operation select bit 0 : Count stops at compare match w ith
TRD1 count operation select bit 0 : Count stops at compare match w ith
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Timer RD synchronous bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRDGRC0 register function
select bit
TRDGRD0 register function
select bit
TRDGRC1 register function
select bit
TRDGRD1 register function
select bit
Address
Bit Name
Address
Bit Name
0137h
0138h
(4)
(5)
0 : Count stops
1 : Count starts
0 : Count stops
1 : Count starts
1 : Count continues at compare match w ith
1 : Count continues at compare match w ith
0 : Registers TRD0 and TRD1 operate
1 : Registers TRD0 and TRD1 operate
0 : General register
1 : Buffer register of TRDGRA0 register
0 : General register
1 : Buffer register of TRDGRB0 register
0 : General register
1 : Buffer register of TRDGRA1 register
0 : General register
1 : Buffer register of TRDGRB1 register
the TRDGRA0 register
the TRDGRA0 register
the TRDGRA1 register
the TRDGRA1 register
independently
synchronously
(2)
(3)
After Reset
After Reset
11111100b
00001110b
Function
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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