MC56F8037VLH Freescale Semiconductor, MC56F8037VLH Datasheet - Page 111

• Manufacturer Part Number: MC56F8037VLH
• Description: IC DSP 16BIT DUAL 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8037VLH

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• Package: 64LQFP
• Family Name: 56F8xxx
• Maximum Speed: 32 MHz
• On-chip Adc: 2(8-chx10-bit)
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 5
• For Use With: MC56F8037EVM - BOARD EVAL FOR MC56F8037
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.14.1
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.3.15
This register provides write protection of selected control fields for safety-critical applications. The
primary purpose is to prevent unsafe conditions due to the unintentional modification of these fields
between the onset of a code runaway and a reset by the COP watchdog. The GPIO and Internal Peripheral
Select Protection (GIPSP) field protects the contents of registers in the SIM and GPIO modules that control
inter-peripheral signal muxing and GPIO configuration. The Peripheral Clock Enable Protection (PCEP)
field protects the SIM registers’ contents, which contain peripheral clock controls. Some peripherals
provide additional safety features. Refer to the 56F802x and 56F803x Peripheral Reference Manual for
details.
Flexibility is provided so that write protection control values may themselves be optionally locked
(write-protected). Protection controls in this register have two bit values which determine the setting of the
control and whether the value is locked. While a protection control remains unlocked, protection can be
disabled and re-enabled by software. Once a protection control is locked, its value can only be altered by
a chip reset, which restores its default non-locked value.
6.3.15.1
This bit field is reserved. Each bit must be set to 0.
6.3.15.2
These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.
Freescale Semiconductor
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Base + $12
Base + $11
RESET
RESET
00 = Write protection off (default)
01 = Write protection on
10 = Write protection off and locked until chip reset
Write
Read
Write
Read
Protection Register (SIM_PROT)
Figure 6-16 I/O Short Address Location Low Register (SIM_IOSALO)
Input/Output Short Address Location (ISAL[21:6])—Bits 15–0
Reserved—Bits 15–4
Peripheral Clock Enable Protection (PCEP)—Bits 3–2
15
0
0
15
1
14
0
0
14
1
Figure 6-17 Protection Register (SIM_PROT)
13
0
0
13
1
12
0
0
12
1
56F8037/56F8027 Data Sheet, Rev. 7
11
0
0
11
1
10
0
0
10
1
9
0
0
9
1
8
0
0
8
ISAL[21:6]
1
7
0
0
7
1
6
6
1
0
0
5
1
5
0
0
4
1
4
0
0
3
1
3
0
PCEP
2
1
2
0
Register Descriptions
1
0
1
1
GIPSP
0
0
0
1
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