MCF52232CAF50 Freescale Semiconductor, MCF52232CAF50 Datasheet - Page 37

• Manufacturer Part Number: MCF52232CAF50
• Description: IC MCU 32BIT 128K FLASH 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF5223xr

Specifications of MCF52232CAF50

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Cpu Family: MCF5223x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Interface Type: I2C/QSPI/UART
• Total Internal Ram Size: 32KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 10
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 8-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Processor Series: MCF522x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 10
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52235EVB, M52233DEMO
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Figure 8
Freescale Semiconductor
shows timing for the values in
SDA
SCL
1
2
3
Num
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
Specified at a nominal 50-pF load.
I1
I2
I3
I4
I5
I6
I7
I8
I9
1
1
2
1
3
1
1
1
1
Table 29. I
Start condition hold time
Clock low period
I2C_SCL/I2C_SDA rise time
(V
Data hold time
I2C_SCL/I2C_SDA fall time
(V
Clock high time
Data setup time
Start condition setup time (for repeated start
condition only)
Stop condition setup time
I1
IL
IH
= 0.5 V to V
= 2.4 V to V
2
C Output Timing Specifications between I2C_SCL and I2C_SDA
I2
MCF52235 ColdFire Microcontroller Data Sheet, Rev. 10
IH
IL
Characteristic
Table 28
= 2.4 V)
= 0.5 V)
I4
Figure 8. I
Table 29
and
Table
I6
are minimum values.
2
C Input/Output Timings
29.
I7
10  t
10  t
20 x t
10 x t
6  t
7  t
2  t
Min
—
—
CYC
CYC
CYC
I8
CYC
CYC
CYC
CYC
Max
—
—
—
—
—
—
—
—
3
I5
I3
Table
Electrical Characteristics
29. The I
Units
ns
ns
µs
ns
ns
ns
ns
ns
ns
I9
2
C
37