SAB-C161PI-LF CA Infineon Technologies, SAB-C161PI-LF CA Datasheet - Page 10

• Manufacturer Part Number: SAB-C161PI-LF CA
• Description: IC MICROCONTROLLER 16BIT 100TQFP
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161PI-LF CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LFQFP
• Packages: PG-TQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: B161PILFCAXT; SAB-C161PI-LF CA; SAB-C161PI-LFCAINTR; SABC161PILFCAXT; SP000014344

Data Sheet
Table 1
Symbol Pin
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
RD
WR/
WRL
READY 33
ALE
Num.
TQFP
24
25
26
27
28
29
30
31
32
34
Pin Definitions and Functions (continued)
Pin
Num.
MQFP
26
27
28
29
30
31
32
33
34
35
36
Input
Outp.
IO
O
O
O
O
O
O
O
O
O
I
O
Function
Port 4 is a 7-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For
a pin configured as input, the output driver is put into
high-impedance state. Port 4 outputs can be
configured as push/pull or open drain drivers. The input
threshold of Port 4 is selectable (TTL or special). Port 4
can be used to output the segment address lines:
A16
A17
A18
A19
A20
A21
A22
External Memory Read Strobe. RD is activated for
every external instruction or data read access.
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-
mode this pin is activated for low byte data write
accesses on a 16-bit bus, and for every data write
access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
Ready Input. When the Ready function is enabled, a
high level at this pin during an external memory access
will force the insertion of memory cycle time waitstates
until the pin returns to a low level.
An internal pullup device will hold this pin high when
nothing is driving it.
Address Latch Enable Output. Can be used for latching
the address into external memory or an address latch
in the multiplexed bus modes.
8
Least Significant Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Segment Address Line
Most Significant Segment Address Line
&3,
1999-07