SAB-C161PI-LF CA Infineon Technologies, SAB-C161PI-LF CA Datasheet - Page 48

• Manufacturer Part Number: SAB-C161PI-LF CA
• Description: IC MICROCONTROLLER 16BIT 100TQFP
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161PI-LF CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LFQFP
• Packages: PG-TQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: B161PILFCAXT; SAB-C161PI-LF CA; SAB-C161PI-LFCAINTR; SABC161PILFCAXT; SP000014344

Data Sheet
Table 8
P0.15-13
(P0H.7-5)
1) The external clock input range refers to a CPU clock range of 10...25 MHz.
2) The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation
When pins P0.15-13 (P0H.7-5) equal 001
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
the duration of an individual TCL) is defined by the period of the input clock
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
Phase Locked Loop
For all combinations of pins P0.15-13 (P0H.7-5) except for 001
phase locked loop is enabled and provides the CPU clock (see table above). The PLL
multiplies the input frequency by the factor F which is selected via the combination of
pins P0.15-13 (i.e.
synchronizes the CPU clock to the input clock. This synchronization is done smoothly,
i.e. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
it is locked to
duration of individual TCLs.
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
CPU Frequency
I
CPU
C161PI Clock Generation Modes
OSC
=
OSC
OSC
CPU
OSC
OSC
OSC
OSC
OSC
OSC
. The slight variation causes a jitter of
I
OSC
CPU
* 1.5
* 2.5
is half the frequency of
* 4
* 3
* 2
* 5
* 1
/ 2
* F
=
OSC
OSC
External Clock
Input Range
2.5 to 6.25 MHz
3.33 to 8.33 MHz
5 to 12.5 MHz
2 to 5 MHz
1 to 25 MHz
6.66 to 16.6 MHz
2 to 50 MHz
4 to 10 MHz
* F). With every F’th transition of
for any TCL.
B
46
during reset the CPU clock is derived from
1)
OSC
and the high and low time of
Notes
Direct drive
Default configuration
CPU clock via prescaler
CPU
CPU
is constantly adjusted so
B
which also effects the
2)
and 011
OSC
the PLL circuit
B
the on-chip
OSC
&3,
CPU
.
1999-07
(i.e.