PIC14000-04/SS Microchip Technology, PIC14000-04/SS Datasheet - Page 38

• Manufacturer Part Number: PIC14000-04/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000-04/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC14000
6.1
The TMR0 interrupt is generated when the Timer0
overflows from FFh to 00h. This overflow sets the T0IF
bit. The interrupt can be masked by clearing bit T0IE
(INTCON<5>). Flag bit T0IF (INTCON<2>) must be
cleared in software by the TMR0 module interrupt ser-
FIGURE 6-2:
FIGURE 6-3:
FIGURE 6-4:
DS40122B-page 38
INSTRUCTION FLOW
GIE bit
(INTCON<7>)
T0IF bit
(INTCON<2>)
PC
(Program
Counter)
Instruction
Fetch
TMR0
Instruction
Execute
Instruction
fetched
Instruction
PC
(Program
Counter)
Fetch
TMR0
Instruction
executed
Instruction
Executed
TMR0 timer
CLKOUT(3)
OSC1
Timer0 Interrupt
PC
Note 1: T0IF interrupt flag is sampled here (every Q1).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
T0
Q1
2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in HS oscillator mode.
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TIMER0 INTERRUPT TIMING
PC-1
PC-1
FEh
Inst (PC)
Inst (PC-1)
Q2
PC
1
Q3
MOVWF TMR0
MOVWF TMR0
T0+1
PC
Q4
PC
T0+1
Q1
FFh
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed
Inst (PC+1)
1
T0+2
Write TMR0
executed
Inst (PC)
Q2
PC +1
PC+1
PC+1
Q3
Preliminary
Q4
Read TMR0
reads NT0
NT0
Read TMR0
reads NT0
PC+2
PC+2
Q1
00h
Dummy cycle
Q2
PC +1
vice routine before re-enabling this interrupt. The
Timer0 module interrupt cannot wake the processor
from SLEEP since the timer is shut off during SLEEP.
The timing of the Timer0 interrupt is shown in
Figure 6-4.
Read TMR0
reads NT0
NT0
Read TMR0
reads NT0
Q3
PC+3
PC+3
NT0
Q4
Q1
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0
01h
Dummy cycle
PC+4
Inst (0004h)
PC+4
Q2
0004h
Q3
MOVF TMR0,W
MOVF TMR0,W
1996 Microchip Technology Inc.
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
NT0+1
Q4
PC+5
PC+5
Q1
02h
Inst (0004h)
Inst (0005h)
Q2
Read TMR0
reads NT0 + 1
0005h
Read TMR0
reads NT0 + 2
NT0+1
NT0+2
PC+6
PC+6
Q3
Q4