PIC14000-04/SS Microchip Technology, PIC14000-04/SS Datasheet - Page 51

• Manufacturer Part Number: PIC14000-04/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000-04/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.5.1.3
When the R/W bit of the address byte is set and an
address match occurs, the R/W bit of the I
register is set. The received address is loaded into the
I
the SCL pin is held low. The transmit data must be
loaded into the I
I
setting the CKP bit (I
are shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 7-15).
FIGURE 7-15: I
2
2
CBUF The ACK pulse will be sent on the ninth bit, and
CSR register. Then the SCL pin should be enabled by
1996 Microchip Technology Inc.
SDA
SCL
I
BF (I
CKP (I
2
CIF (PIR1<3>)
2
CSTAT<0>)
2
CCON<4>)
TRANSMISSION
S
2
CBUF register, which also loads the
2
A7
1
Data in
sampled
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
2
CCON<4>). The eight data bits
A6
2
A5
Receiving Address
3
A4 A3
4
5
A2
6
A1
7
2
CSTAT
R/W = 1
8
Preliminary
9
ACK
responds to I
while CPU
SCL held low
A I
byte. The I
I
byte. The I
clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line was high (not
ACK), then the data transfer is complete. The slave
then monitors for another occurrence of the START bit.
If the SDA line was low (ACK), the transmit data must
be loaded into the I
the I
enabled by setting the CKP bit (I
2
CSTAT register is used to determine the status of the
2
CIF
2
CIF interrupt is generated for each data transfer
D7
1
I
2
2
CSR register. Then the SCL pin should be
CBUF is written in software
D6
cleared in software
2
2
2
Set bit after writing to I
CIF bit must be cleared in software, and the
CIF bit is set on the falling edge of the ninth
D5
3
D4 D3
4
2
Transmitting Data
CBUF register, which also loads
5
D2
6
2
From I
service routine
D1
CBUF
PIC14000
7
2
CCON<4>).
D0
2
8
CIF interrupt
DS40122B-page 51
ACK
9
P