PIC14000-04/SS Microchip Technology, PIC14000-04/SS Datasheet - Page 48

• Manufacturer Part Number: PIC14000-04/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000-04/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC14000
FIGURE 7-13:
7.5
The I
functions, and provides support in hardware to facilitate
software implementations of the master functions. The
I
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC6/SCLA pin, which is the I
RC7/SDAA pin which acts as the I
module can also be accessed via the RD0/SCLB and
RD1/SDAB pins by setting I
user must configure these pins as inputs or outputs
through the TRISC<7:6> or TRISD<1:0> bits. A block
diagram of the I
Figure 7-13. The I
setting the I
The I
These are the:
• I
• I
• Serial Receive/Transmit Buffer (I
• I
• Address Register (I
The I
operation. Four mode selection bits (I
allow one of the following I
• I
• I
DS40122B-page 48
2
C module implements the standard and fast mode
accessible
2
2
2
2
2
C Control Register (I
C Status Register (I
C Shift Register (I
C Slave mode (7-bit address)
C Slave mode (10-bit address)
2
2
2
C module in I
C module has five registers for I
CCON register (14h) allows control of the I
RC7/SDAA
RD1/SDAB
RC6/SCLA
RD0/SCLB
I
2
C Operation
2
CCON<5> bit.
2
C module in I
2
I
C module functions are enabled by
2
2
C BLOCK DIAGRAM
C mode fully implements all slave
2
2
CADD)
CSR) - Not directly
2
2
CSTAT)
CCON)
2
C modes to be selected:
2
MISC<4>
CSEL (MISC<4>).The
2
MUX
C mode is shown in
4:2
2
2
C clock, and the
CBUF)
2
C data. The I
2
SCK
SDA
2
CCON<3:0>)
C operation.
Preliminary
2
2
C
C
Read
Shift
clock
MSB
• I
• I
• I
Selection of any I
the SCL and SDA pins to be open collector, provided
these pins are set to inputs through the TRISC bits.
The I
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address, if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer. The I
The I
written to or read from. The I
data in or out of the device. In receive operations, the
I
This allows reception of the next byte before reading
the last byte of received data. When the complete byte
is received, it is transferred to the I
is set. If another complete byte is received before the
I
the I
The I
mode, the user needs to write the high byte of the
address (1 1 1 1 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7-A0).
2
2
CBUF and I
CBUF is read, a receiver overflow has occurred and
Stop bit detect
stop bit interrupts enabled
stop bit interrupts enabled
idle
2
2
2
Match Detect
C Slave mode (7-bit address), with start and
C Slave mode (10-bit address), with start and
C Firmware Controlled Master mode, slave is
I
2
2
Start and
2
2
CCON<6> is set.
CBUF
I
2
I
CADD register holds the slave address. In 10-bit
2
CBUF is the register to which transfer data is
2
CSTAT register gives the status of the data
CADD
CSR
2
2
CSR create a double buffered receiver.
CSTAT register is read only.
Write
2
C mode with the I
data bus
Internal
1996 Microchip Technology Inc.
(I
Addr_Match
2
Set, Reset
CSTAT Reg)
S, P bits
2
CSR register shifts the
2
CBUF and PIR1<3>
2
CEN bit set, forces