EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 11

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

Chapter 17. IrDA .................................................................................................. 17-1
Chapter 18. Timers .............................................................................................. 18-1
Chapter 19. Watchdog Timer.............................................................................. 19-1
DS785UM1
19.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-3
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1
17.2 IrDA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-1
17.3 Shared IrDA Interface Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-2
17.4 Medium IrDA Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-8
17.5 Fast IrDA Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-13
17.6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17-23
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1
18.2 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-2
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1
17.3.1 Overview......................................................................................................................17-2
17.3.2 Functional Description .................................................................................................17-2
17.3.3 Control Information Buffering.......................................................................................17-8
17.4.1 Introduction..................................................................................................................17-8
17.4.2 Functional Description ...............................................................................................17-11
17.5.1 Introduction................................................................................................................17-14
17.5.2 Functional Description ...............................................................................................17-17
17.5.3 IrDA Connectivity.......................................................................................................17-20
17.5.4 IrDA Integration Information ......................................................................................17-21
18.1.1 Features ......................................................................................................................18-1
18.1.2 16 and 32-bit Timer Operation.....................................................................................18-1
18.1.3 40-bit Timer Operation.................................................................................................18-2
19.1.1 Watchdog Activation....................................................................................................19-2
19.1.2 Clocking Requirements ...............................................................................................19-2
19.1.3 Reset Requirements....................................................................................................19-2
19.1.4 Watchdog Status .........................................................................................................19-2
17.3.2.1 General Configuration................................................................................17-3
17.3.2.2 Transmitting Data ......................................................................................17-3
17.3.2.3 Receiving Data ..........................................................................................17-5
17.3.2.4 Special Conditions .....................................................................................17-7
17.4.1.1 Bit Encoding...............................................................................................17-8
17.4.1.2 Frame Format ............................................................................................17-9
17.4.2.1 Baud Rate Generation .............................................................................17-11
17.4.2.2 Receive Operation ...................................................................................17-11
17.4.2.3 Transmit Operation ..................................................................................17-13
17.5.1.1 4PPM Modulation ....................................................................................17-14
17.5.1.2 4.0 Mbps FIR Frame Format ...................................................................17-15
17.5.2.1 Baud Rate Generation .............................................................................17-17
17.5.2.2 Receive Operation ...................................................................................17-18
17.5.2.3 Transmit Operation ..................................................................................17-19
17.5.4.1 Enabling Infrared Modes..........................................................................17-21
17.5.4.2 Clocking Requirements............................................................................17-21
17.5.4.3 Bus Bandwidth Requirements .................................................................17-22
18.1.2.1 Free Running Mode ...................................................................................18-2
18.1.2.2 Pre-load Mode ...........................................................................................18-2
©
Copyright 2007 Cirrus Logic, Inc.
EP93xx User’s Guide
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