EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 408

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

10
10-14
DMA Controller
EP93xx User’s Guide
The DMA Controller initiates memory-to-memory transfers in the receive direction (that is,
from memory/peripheral to DMA) under the following circumstances:
The DMA Controller initiates memory-to-memory transfers in the transmit direction (that is,
from DMA to memory/external bus) under the following circumstances:
• A channel has been triggered by software, that is, setting the START bit to “1”. Setting
• A channel receives a transfer request from SSP or IDE or an external device without
• A channel receives a request from an external device and the transfer mode is set to be
• When the current transfer terminates the DMA will check if the BCR register for the
the START bit causes the channel to begin requesting the bus, and when granted
ownership it will start transferring data immediately. The DMA controller drives the
SAR_BASEx value onto the internal AHB address bus. If CONTROL.SCT is not set, the
SAR_BASEx increments by the appropriate number of bytes upon a successful read
cycle. The DMA initiates the write portion of the transfer when the appropriate number of
read cycles is completed, that is, either when the 16-byte data bay has been filled, or
when it contains the number of bytes (less than 16) that remain to be transferred, or
when it contains sufficient data for an unaligned byte/word access (dependant on the
next address access).
handshaking signals (that is, CONTROL.NO_HDSK = “1”), and the transfer mode is set
to be either memory-to-external bus mode or external device-to-memory mode (that is,
CONTROL.TM = “01”/“10” respectively). The DMA drives the SAR_BASEx value onto
the address bus and requests a transfer size equal to the programmed peripheral width.
In the case of CONTROL.TM = “10” where the external device (which is the source for
the data) is FIFO-based, it is up to software to program the SAH bit correctly (Source
Address Hold), so that on successive transfers from the peripheral, the
SAR_CURRENTx value will not increment, thus reflecting the FIFO-nature of the
peripheral.
either memory-to-external device mode or external device-to-memory mode (that is,
CONTROL.TM = “01” or “10” respectively). The DMA drives the SAR_BASEx value onto
the address bus and requests a transfer size equal to the programmed peripheral width.
In the case of CONTROL.TM = “10” where the external device (which is the source for
the data) is FIFO-based, it is up to software to program the SAH bit correctly (Source
Address Hold), so that on successive transfers from the peripheral, the
SAR_CURRENTx value will not increment, thus reflecting the FIFO-nature of the
peripheral.
“other” buffer (of the double-buffer set) has been programmed. If BCR is non-zero and
CONTROL.TM = “00”, that is, software trigger mode, then the DMA will proceed
immediately to request the AHB bus and begin a transfer from memory to DMA using
the other buffer descriptor. Software does not need to reprogram the START bit, it is
enough to have the second buffer descriptor set up while the first buffer transfer is in
progress. In the case where TM is such that external-device mode is set up, then
rollover to the other buffer will also occur if the current transfer terminates, but the DMA
will wait until it receives a DREQ from the external peripheral before initiating a transfer.
Copyright 2007 Cirrus Logic
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