EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 445

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
scheduling the Endpoint Descriptor at the appropriate depth in the tree. The higher the polling
rate, the closer to the root of the tree the Endpoint Descriptor will be placed since multiple
lists will converge on it.
Interrupt Endpoint Descriptor Placeholder indicates where zero or more Endpoint Descriptors
may be enqueued. The numbers on the left are the index into the HCCA interrupt head
pointer array.
Figure 11-5
Descriptors at a 1 ms poll interval, two Endpoint Descriptors at a 2 ms poll interval, one
Endpoint at a 4 ms poll interval, two Endpoint Descriptors at an 8 ms poll interval, two
Endpoint Descriptors at a 16 ms poll interval, and two Endpoint Descriptors at a 32 ms poll
interval. Note that in this example unused Interrupt Endpoint Placeholders are bypassed and
the link is connected to the next available Endpoint in the hierarchy.
Interrupt
Head
Pointers
is a sample Interrupt Endpoint schedule. The schedule shows one Endpoint
16
24
20
12
28
18
10
26
22
14
30
17
25
21
13
29
19
27
23
15
31
11
0
8
4
2
6
1
9
5
3
7
Figure 11-4. Interrupt Endpoint Descriptor Structure
32
Figure 11-4
Interrupt Endpoint Descriptor Placeholders
Copyright 2007 Cirrus Logic
16
Endpoint Poll Interval (ms)
illustrates the structure for Interrupt Endpoints. The
8
4
Universal Serial Bus Host Controller
2
EP93xx User’s Guide
1
11-5
11