EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 411

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

DS785UM1
10.1.11 DMA Data Transfer Size Determination
10.1.11.1 Software Initiated M2M and M2P/P2M Transfers
DREQ_SYNC1
DREQ_SYNC2
Data transfer size flexibility is guaranteed by allowing the start address of a DMA transfer to
be aligned to any arbitrary byte boundary since this is the case for the 10 internal byte-wide
M2P/P2M channels and for the 2 M2M channels when used in software initiated mode.
HCLK
EXDREQ
LATCH_DREQ
DREQ
DMA_STATE
1. A DREQ rising edge (DREQ is active high) is latched onto LATCH_DREQ during cycle
2. This signal is synchronized using 2 HCLK flip-flops. The DREQS status bit indicates a
3. The DMA state machine moves into the DMA_MEM_RD state to begin servicing the first
4. The DREQ latch is reset as a result of this state change and 2 cycles later the DREQS
5. A second request cannot be recognized until DREQS is cleared. Hence the request
6. A rising edge on DREQ during cycle 6 is latched and causes the DREQS status bit to be
1.
Subsequent changes on DREQ are ignored until the pending request begins to be
serviced. When the pending request has begun to be serviced, the DREQS status bit is
cleared and subsequent edge-triggered requests are again recognized (latched) by the
DMA. The DREQS status bit can be cleared by a software write to the channel STATUS
register, thus causing the DMA to ignore the request.
request is pending at start of cycle 3.
request in cycle 4.
status bit is cleared.
received during cycle 2 is ignored by the DMA.
set again, thus indicating that another external peripheral request is pending.
1
DMA_STALL
2
Figure 10-4. Edge-triggered DREQ Mode
Copyright 2007 Cirrus Logic
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4
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DMA_MEM_RD
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EP93xx User’s Guide
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DMA Controller
10-17
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