EP9302-IQZ Cirrus Logic Inc, EP9302-IQZ Datasheet - Page 4

• Manufacturer Part Number: EP9302-IQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-IQZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Digital Ic Case Style: LQFP
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1253

EP93xx User’s Guide
Chapter 3. MaverickCrunch Co-Processor ......................................................... 3-1
Chapter 4. Boot ROM ............................................................................................ 4-1
iv
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.2 Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.3 DSPSC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
3.4 ARM Co-Processor Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.5 Instruction Set for the MaverickCrunch Co-Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.2 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
2.3.2 AHB-to-APB Bridge .......................................................................................................2-12
2.3.3 APB Slave .....................................................................................................................2-13
2.3.4 Register Definitions .......................................................................................................2-13
2.3.5 Memory Map..................................................................................................................2-16
2.3.6 Internal Register Map ....................................................................................................2-17
3.1.1 Features ..........................................................................................................................3-1
3.1.2 Operational Overview ......................................................................................................3-1
3.1.3 Pipelines and Latency .....................................................................................................3-3
3.1.4 Data Registers.................................................................................................................3-3
3.1.5 Integer Saturation Arithmetic ...........................................................................................3-4
3.1.6 Comparisons ...................................................................................................................3-6
3.2.1 Example 1........................................................................................................................3-8
3.2.2 Example 2........................................................................................................................3-9
3.5.1 Load and Store Instructions...........................................................................................3-21
3.5.2 Move Instructions ..........................................................................................................3-24
3.5.3 Accumulator and DSPSC Move Instructions .................................................................3-27
3.5.4 Copy and Conversion Instructions.................................................................................3-31
3.5.5 Shift Instructions ............................................................................................................3-35
3.5.6 Compare Instructions ....................................................................................................3-36
3.5.7 Floating Point Arithmetic Instructions ............................................................................3-38
3.5.8 Integer Arithmetic Instructions .......................................................................................3-41
3.5.9 Accumulator Arithmetic Instructions ..............................................................................3-45
4.1.1 Boot ROM Hardware Operational Overview....................................................................4-1
4.1.2 Boot ROM Software Operational Overview .....................................................................4-1
4.2.1 UART Boot ......................................................................................................................4-6
4.2.2 SPI Boot ..........................................................................................................................4-6
4.2.3 FLASH Boot.....................................................................................................................4-6
4.2.4 SDRAM or SyncFLASH Boot ..........................................................................................4-7
2.3.2.1 Function and Operation of the AHB-to-APB Bridge.....................................2-12
2.3.6.1 Memory Access Rules .................................................................................2-17
3.2.1.1 Setup Code....................................................................................................3-8
3.2.1.2 C Code...........................................................................................................3-8
3.2.1.3 Accessing MaverickCrunch with ARM Co-Processor Instructions.................3-8
3.2.1.4 MaverickCrunch Assembly Language Instructions ........................................3-8
3.2.2.1 C Code...........................................................................................................3-9
3.2.2.2 MaverickCrunch Assembly Language Instructions ........................................3-9
4.1.1.1 Memory Map..................................................................................................4-1
4.1.2.1 Image Header ................................................................................................4-2
4.1.2.2 Boot Algorithm ...............................................................................................4-2
4.1.2.3 Flowchart .......................................................................................................4-3
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Copyright 2007 Cirrus Logic, Inc.
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