Z16F2810VH20SG Zilog, Z16F2810VH20SG Datasheet - Page 135

• Manufacturer Part Number: Z16F2810VH20SG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4536

PS022008-0810
Synchronization of PWM and ADC
Synchronized Current-Sense Sample and Hold
PWM Timer and Fault Interrupts
Fault Detection and Protection
programmed duty cycle is greater than the threshold but the decrease in pulse width
because of deadband insertion causes the pulse to be too narrow. The pulse width filter
value is calculated as:
where
The ADC on the ZNEO is synchronized with the PWM period. Enabling the PWM ADC
trigger causes the PWM to generate an ADC conversion signal at the end of each PWM
period. Additionally, in CENTER-ALINGED mode, the PWM generates a trigger at the
center of the period. Setting the ADCTRIG bit in the
(PWMCTL0)
The PWM controls the current-sense input sample and hold amplifier. The signal
controlling the sample/hold is configured to always sample or automatically hold when
any or all the PWM High or Low outputs are in the on state. The current-sense sample and
hold is controlled by the
CSSHR1).
The PWM generates interrupts to the ZNEO CPU during any of the following events:
•
•
The ZNEO contains hardware and software fault controls, which allow rapid deassertion
of all enabled PWM output signals. A logic Low on an external fault pin (FAULT0 or
FAULT1) or the assertion of the over current comparator forces the PWM outputs to the
predefined off-state.
Similar deassertion of the PWM outputs is accomplished in software by writing to the
PWMOFF bit in the PWM control 0 register. The PWM counter continues to operate
while the outputs are deasserted (inactive) due to one of these fault conditions.
PWM Reload—The interrupt is generated at the end of a PWM period when a PWM
PWM Fault—A fault condition is indicated by asserting any FAULT pins or by the
register reload occurs.
assertion of the comparator.
T
roundup PWMMPF
minPulseOut
enables the ADC synchronization.

is the shortest allowed pulse width on the PWM outputs (in seconds).
Current-Sense Sample and Hold Control Register (CSSHR0 and

P R E L I M I N A R Y
=
T
minPulseOut


T
systemClock
PWM Control 0 Register

PWMprescaler
Multi-Channel PWM Timer
Product Specification
ZNEO

Z16F Series
120